Data Sheet

WL1801MOD,
WL1805MO
D
,
WL1831MO
D
,
WL1835MOD
SWRS152M – JULY 2013 – REVISED OCTOBER 2017
www.ti.com
Specifications 21
Copyright © 2013–2017, Texas Instruments Incorporated
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WL1835MOD
5.19.6.2 SDIO Switching Characteristics – High Rate
Figure 5-8 and Figure 5-9 show the parameters for maximum clock frequency.
V
DD
Clock Input
V
IH
t
WL
t
WH
V
IH
V
IH
50% V
DD
V
IL
V
IL
V
SS
V
DD
t
THL
t
TLH
t
ISU
t
IH
V
IH
V
IH
Data Input
V
SS
Not Valid
Valid
V
IL
V
IL
Not Valid
Figure 5-8. SDIO HS Input
Timing
V
DD
Clock Input
V
SS
50% V
DD
t
THL
V
IH
V
IL
t
WL
V
IL
t
WH
V
IH
V
IH
50% V
DD
t
TLH
V
DD
t
ODLY(max)
t
OH(min)
Data Output
V
SS
Not Valid
V
OH
V
OL
Valid
V
OH
V
OL
Not Valid
Figure 5-9. SDIO HS Output
Timing
Table 5-2 lists the SDIO high-rate timing characteristics.
Table 5-2. SDIO HS Timing
Characteristics
MIN MAX
UNIT
f
clock
Clock frequency, CLK 0.0 52.0 MHz
DC Low, high duty cycle 40.0% 60.0%
t
TLH
Rise time, CLK
3.0
ns
t
THL
Fall time, CLK
3.0
ns
t
ISU
Setup time, input valid before CLK ↑
3.0
ns
t
IH
Hold time, input valid after CLK ↑
2.0
ns
t
ODLY
Delay time, CLK ↑ to output valid 7.0 10.0 ns
C
l
Capacitive load on outputs
10.0 pF