Data Sheet

WL1801MOD,
WL1805MO
D
,
WL1831MO
D
,
WL1835MOD
SWRS152M – JULY 2013 – REVISED OCTOBER 2017
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20 Specifications
Copyright © 2013–2017, Texas Instruments Incorporated
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WL1835MOD
5.19.6 WLAN SDIO Transport Layer
The SDIO is the host interface for WLAN. The interface between the host and the WL18xx module uses
an SDIO interface and supports a maximum clock rate of 50 MHz.
The device SDIO also supports the following features of the SDIO V3 specification:
• 4-bit data bus
• Synchronous and asynchronous in-band interrupt
• Default and high-speed (HS, 50 MHz) timing
• Sleep and wake commands
5.19.6.1 SDIO Timing Specifications
Figure 5-6 and Figure 5-7 show the SDIO switching characteristics over recommended operating
conditions and with the default rate for input and output.
V
DD
Clock
Input
V
IH
t
WL
t
WH
V
IH
V
IH
V
SS
V
IL
V
IL
t
THL
t
TLH
V
DD
Data Input
V
SS
Not Valid
t
ISU
V
IH
V
IH
Valid
V
IL
V
IL
t
IH
Not Valid
Figure 5-6. SDIO Default Input Timing
V
DD
Clock Input
V
SS
V
DD
Data
Output
V
SS
t
THL
V
IH
Not Valid
t
WL
V
IL
V
IL
t
ODLY(max)
V
OH
V
OL
t
WH
V
IH
V
IH
t
TLH
V
OH
Valid
V
OL
t
ODLY(min)
Not Valid
Figure 5-7. SDIO Default Output
Timing
Table 5-1 lists the SDIO default timing characteristics.
Table 5-1. SDIO Default Timing
Characteristics
(1)
MIN MAX
UNIT
f
clock
Clock frequency,
CLK
(2)
0.0 26.0 MHz
DC Low, high duty cycle
(2)
40.0% 60.0%
t
TLH
Rise time,
CLK
(2)
10.0
ns
t
THL
Fall time,
CLK
(2)
10.0
ns
t
ISU
Setup time, input valid before CLK ↑
(2)
3.0
ns
t
IH
Hold time, input valid after CLK ↑
(2)
2.0
ns
t
ODLY
Delay time, CLK ↓ to output valid
(2)
7.0 10.0 ns
C
l
Capacitive load on
outputs
(2)
15.0 pF
(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.
(2) Parameter values reflect maximum clock frequency.