Data Sheet

WL1801MOD,
WL1805MO
D
,
WL1831MO
D
,
WL1835MOD
SWRS152M – JULY 2013 – REVISED OCTOBER 2017
www.ti.com
18 Specifications
Copyright © 2013–2017, Texas Instruments Incorporated
Submit Documentation
Feedback
Product Folder Links: WL1801MOD WL1805MOD WL1831MOD
WL1835MOD
To perform the correct power-up sequence, assert (high) WL_EN. The internal DC-DCs, LDOs, and clock
start to ramp and stabilize. Stable slow clock, V
IO
, and V
BAT
are prerequisites to the assertion of one of the
enable signals.
To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device
(V
BAT
, V
IO
, and slow clock) are still stable and available. The supplies to the chip (V
BAT
and V
IO
) can be
deasserted only after both enable signals are deasserted (low).
Figure 5-2 shows the general power scheme for the module, including the power-down sequence.
VBAT
1
VIO
5 5
EXT_32K
>10 µs 2
>10 µs 4
WLEN
3
>
60 µs
NOTE: 1. Either VBAT or VIO can come up first.
2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times
when the EN is active.
3. At least 60 µs is required between two successive device enables. The device is assumed to be in
shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.
4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered (order of supply turn off
after EN shutdown is immaterial).
5. EXT_32K - Fail safe I/O
Figure 5-2. Power-Up
System
5.19.3 Chip Top-level Power-Up Sequence
Figure 5-3 shows the top-level power-up sequence for the chip.
VBAT
/
VIO
input
EXT_32K
input
WL_EN
input
Main 1V8
DC2DC
4.5 ms
delay
DIG
DC2DC
SRAM LDO
Top
RESETZ
TCXO_CLK_REQ
output
Internal power
stable
= 5
ms
Figure 5-3. Chip Top-Level Power-Up Sequence