Data Sheet

WL1801MOD,
WL1805MO
D
,
WL1831MO
D
,
WL1835MOD
SWRS152M – JULY 2013 – REVISED OCTOBER 2017
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10 Specifications
Copyright © 2013–2017, Texas Instruments Incorporated
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Product Folder Links: WL1801MOD WL1805MOD WL1831MOD
WL1835MOD
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Ambient operating temperature –20 70 ºC
Maximum power
dissipation
WLAN operation
2.8 W
Bluetooth operation
0.2
5.4 External Digital Slow Clock Requirements
The supported digital slow clock is 32.768 kHz digital (square wave). All core functions share a single input.
CONDITION MIN TYP MAX UNIT
Input slow clock frequency 32768 Hz
Input slow clock accuracy (Initial + temp +
aging)
WLAN,
Bluetooth
±
250 ppm
T
r
, T
f
Input transition time (10% to 90%) 200 ns
Frequency input duty cycle 15% 50% 85%
V
IH
, V
IL
Input voltage limits
Square
wave, DC-
coupled
0.65 x VDD_IO VDD_IO
V
peak
0 0.35 x VDD_IO
Input impedance 1 MΩ
Input capacitance 5
pF
5.5 Thermal Resistance Characteristics for MOC 100-Pin Package
THERMAL
METRICS
(1)
(
°C/W)
(2)
θ
JA
Junction to free air
(3)
16.6
θ
JB
Junction to board
6.06
θ
JC
Junction to case
(4)
5.13
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(3) According to the JEDEC EIA/JESD 51 document
(4) Modeled using the JEDEC 2s2p thermal test board with 36 thermal vias