User Guide

U1
WL1835MODGA
E-13.4X13.3-N100_0.75-TOP
WL_BG ANT2
WL_BG/BT ANT1
Short PIN Header (1-2)
for entering test mode.
Open for function mode.
These two TPs for test mode
when WL_IRQ pull high.
EDGE CONNECTOR - MALE
J5
U.FL-R-SMT(10)
U.FL
1
2
3
SDIO_CMD_WL
R28 0R 0402
J2
NU_100pin Micro Edge MEC6
SD-100P
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
R30 0R
0402
SDIO_CLK_WL
ANT2
ANT016008LCD2442MA1
ANT-N3-1.6X0.8MM-B
5G
B2
FEED
A
2.4G
B1
R10 0R
0402
ANT1
ANT016008LCD2442MA1
ANT-N3-1.6X0.8MM-A
5G
B2
FEED
A
2.4G
B1
WLAN_EN_SOC
C12
NU
0402
L1
0402
1.1nH
C8
NU_10pF
0402
R5 NU_0R
0402
J6
U.FL-R-SMT(10)
U.FL
1
2
3
L2
1.5nH
0402
GPIO9
3
GPIO12
5
GPIO11
2
GPIO10
4
GND
17
VIO
38
VBAT
47
EXT_32K
36
BT_AUD_FSY NC
58
BT_AUD_IN
56
BT_AUD_OUT
57
BT_AUD_C LK
60
WL_SDIO_D2
12
WL_SD IO_CLK
8
WL_SDIO_D3
13
WL_SDIO_D0
10
WL_SDIO_D1
11
WL_SDIO_CMD
6
BT_HCI_RTS
50
BT_HCI_RX
53
BT_HCI_TX
52
BT_HCI_CTS
51
GND
16
GPIO_4
25
GPIO_2
26
GPIO_1
27
BT_EN_SOC
41
WLAN_IRQ
14
WLAN_EN_SOC
40
BT_UART_DBG
43
WL_UART_DBG
42
GND
G13
GND
G14
GND
G15
GND
G16
GND
G9
GND
G10
GND
48
GND
G11
GND
G12
VBAT
46
GND
28
GND
G1
GND
G2
GND
G3
GND
G4
GND
G5
GND
G6
GND
G7
GND
G8
2G4_ANT1_WB
32
GND
64
GND
1
GND
20
RESERVED1
21
RESERVED2
22
GND
37
GND
19
RESERVED3
62
GND
G17
GND
G18
GND
G19
GND
G20
GND
G21
GND
G22
GND
G23
GND
G24
GND
G25
GND
G26
GND
G27
GND
G28
GND
G29
GND
G30
GND
G31
GND
G32
GND
G33
GND
G34
GND
G35
GND
23
GND
59
GND
34
GND
29
GND
7
2G4_ANT2_W
18
GND
49
GND
9
GND
31
GND
35
GND
15
GND
55
GND
45
GND
44
GND
30
GND
24
GND
63
GND
61
GND
39
GND
33
GND
54
GND
G36
C5
10pF
0402
C6
10pF
0402
C11
1.2pF
0402
C14
4pF
0402
C10
NU_0.3pF
0402
C9
2pF
0402
VBAT_IN
VIO_IN
BT_FUNC1
C4
0.1uF
0402
C3
0.1uF
0402
R4 0R 0402
J3
HEADER 1x2
H-1X2_2MM
1
2
SLOW_CLK
TP2
1
TP8
1
R6
0R
0402
TP1
1
OSC1
1V8 / 32.768kHz
OSC-3.2X2.5
EN
1
VCC
4
OUT
3
GND
2
R3 0R 0402
J1
HEADER 1x2
H-1X2_2MM
1
2
VBAT_IN
VIO_IN
VIO_IN
WL_UART_DBG
C1
1uF
0402
BT_UART_DBG
BT_EN_SOC
WLAN_EN_SOC
R31
0R
0402
R32
0R
0402
R2 0R 0402
GPIO10
C2
10uF
0603
R1 0R 0402
R29 0R 0402
0RR24 0402
R27 0R 0402
0RR22 0402 R23 0R 0402
J4
HEADER 1x2
H-1X2_2MM
1
2
0RR26 0402
R20 10k
0402
R25 0R 0402
SDIO_D3_WL
GPIO12
SDIO_D2_WL
GPIO11
SDIO_D0_WL
SDIO_D1_WL
GPIO9
WLAN_IRQ
GPIO10
VIO_IN
0RR21 0402
BT_FUNC2
GPIO9
2G4_ANT2_W
R17 0R 0402
TP5
1
R12 0R 0402
WL_RS232_TX
TP4
1
WL_RS232_RX
2G4_ANT1_WB
BT_FUNC1
BT_FUNC2
R13 0R 0402
TP3
1
0RR19 0402
2G4_ANT2_W
WLAN_IRQ
GPIO11
BT_AUD_CLK
BT_AUD_FSY NC
BT_AUD_IN
WL_RS232_TX
WL_RS232_RX
BT_HCI_TX
BT_HCI_RX
BT_HCI_CTS
BT_HCI_RTS
BT_EN_SOC
BT_UART_DBG
SDIO_CLK_WL
SDIO_CMD_WL
SDIO_D0_WL
SDIO_D2_WL
SDIO_D3_WL
SDIO_D1_WL
C13
8pF
0402
GPIO12
R14 0R 0402
R15 0R 0402
R18 0R 0402
R16 0R 0402
TP6
1
R11 0R 0402
BT_HCI_RX
R9 0R 0402
BT_HCI_TX
BT_HCI_CTS
BT_HCI_RTS
BT_AUD_IN
BT_AUD_OUT
BT_AUD_CLK
BT_AUD_FSY NC
R8 0R 0402
R7 0R 0402
2G4_ANT1_WB
BT_AUD_OUT
SLOW_CLK
C7
NU_10pF
0402
WL_UART_DBG
Circuit Design www.ti.com
6 Circuit Design
6.1 Schematic
Figure 13. Schematic
14
WL1835MODCOM8A WLAN MIMO and BT Module Evaluation Board for TI SWRU359A–September 2013–Revised October 2013
Sitara™ Platform
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated