Datasheet

VSP3200, 3210
14
SBMS012A
OFFSET REGISTER
Offset Registers control the analog offset input to channels
prior to the PGA. There is a 10-bit Offset Register on each
channel. The offset range varies from –500mV to +500mV.
The Offset Register uses a straight binary code. All “0s”
corresponds to –500mV, and all “1s” corresponds to +500mV
of the offset adjustment. The register code (200
H
) corre-
sponds to 0mV of the offset adjustment. The Power-on
default value of the Offset Register is all ”0s”, so the offset
adjustment should be set to –500mV.
PGA GAIN REGISTER
PGA Gain Registers control the gain to channels prior to the
digitization by the A/D converter. There is a 6-bit PGA Gain
Register on each channel. The gain range varies from 1 to
4.8 (from 0dB to 13dB). The PGA Gain Register is a straight
binary code. All “0s” corresponds to an analog gain of 0dB,
and all “1s” corresponds to an analog gain of 13dB. PGA
Transfer function is log gain curve. Power-on default value
is all “0s”, so that it sets the gain of 0dB.
OFFSET AND GAIN CALIBRATION SEQUENCE
When the VSP3200 and VSP3210 are powered on, they will
be initialized as 3-Channel CCDs, 1V internal reference
mode (2V full-scale) with an analog gain of 1, and normal
output mode. This mode is commonly used for CCD scanner
applications. The calibration procedure is done at the very
beginning of the scan.
To calibrate the VSP3200, use the following procedures:
1) Set the VSP3200 to the proper mode.
2) Set Offset to 0mV (control code: 00
H
), and PGA gain to
1 (control code: 200
H
).
3) Scan dark line.
4) Calculate the pixel offsets according to the A/D Converter
output.
5) Readjust input Offset Registers.
6) Scan white line.
7) Calculate gain. It will be the A/D Converter full-scale
divided by the A/D Converter output when the white line
is scanned.
8) Set the Gain Register. If the A/D Converter output is not
close to full-scale, go back to item 3. Otherwise, the
calibration is done.
The calibration procedure is started at the very beginning of
the scan. Once calibration is done, registers on the VSP3200
will keep this information (offset and gain for each channel)
during the operation.
RECOMMENDATION FOR POWER SUPPLY,
GROUNDING, AND DEVICE DECOUPLING
The VSP3200 and VSP3210 incorporate a very-high preci-
sion, high-speed A/D converter and analog circuitry vulner-
able to any extraneous noise from the rails, etc. Therefore, it
should be treated as an analog component and all supply
pins, except V
DRV
, should be powered by the only analog
supply in the system. This will ensure the most consistent
results, since digital power lines often carry high levels of
wideband noise that otherwise would be coupled into the
device and degrade the achievable performance.
Proper grounding, bypassing, short lead length, and the use
of ground planes are particularly important for high-fre-
quency designs. Multilayer PC boards are recommended for
the best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
It is recommended that all ground pins of the VSP3200 and
VSP3210 be joined together at the IC and connected only to
the analog ground of the system. The driver stage of the
digital outputs (B[15:0]) is supplied through a dedicated
supply pin, V
DRV
, and should be completely separated from
other supply pins with at least a ferrite bead. Keeping the
capacitive loading on the output data lines as low as possible
(typically less than 15pF) is also recommended. Larger
capacitive loads demand higher charging current surges that
can feed back into the analog portions of the VSP3200 and
VSP3210, affecting device performance. If possible, exter-
nal buffers or latches should be used, providing the added
benefit of isolating the VSP3200 and VSP3210 from any
digital noise activity on the data lines.
In addition, resistors in series with each data line may help
minimize surge currents. Values in the range of 100W to
200W will limit the instantaneous current the output stage
requires from recharging parasitic capacitances as output
levels change from LOW to HIGH or HIGH to LOW. As the
result of the high operation speed, the converter also gener-
ates high-frequency current transients and noises that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed. In
most cases, 0.1µF ceramic chip capacitors are adequate in
decoupling reference pins. Supply pins should be decoupled
to the ground plane with a parallel combination of tantalum
(1µF to 22µF) and ceramic (0.1µF) capacitors. Decoupling
effectiveness largely depends upon the proximity to the
individual pins.
Not Recommended for New Designs