Datasheet

VSP3200, 3210
12
SBMS012A
INPUT CLAMP
The input clamp should be used for 1-Channel and 3-Channel
CCD mode, and enabled when both CLP and CK1 are set to
HIGH.
Bit Clamp: the input clamp is always enabled.
Line Clamp: enables during the dummy pixel interval at
every horizontal line, and disables during the effective pixel
interval.
Generally, “Bit Clamp” is used for many scanner applica-
tions, however “Line Clamp” is used instead of “Bit Clamp”
when the clamp noise is impressive.
CHOOSING THE AC INPUT COUPLING
CAPACITORS
The purpose of the Input Coupling Capacitor is to isolate the
DC offset of the CCD array from affecting the VSP3200 and
VSP3210 input circuitry. The internal clamping circuitry is
used to restore the necessary DC bias to make the VSP3200
and VSP3210 input circuitry functional. Internal clamp volt-
age, V
CLAMP
, is set when both the CLP pin and CK1 are set
HIGH. V
CLAMP
changes depending on the value of V
REF
.
V
CLAMP
is 2.5V if V
REF
is set to 1V (D1 of the Configuration
Register set to “0”), and V
CLAMP
is 3V if V
REF
is set to 1.5V
(D1 of the Configuration Register set to “1”).
There are many factors that decide what size of Input
Coupling Capacitor is needed. Those factors are CCD signal
swing, voltage difference between the Input Coupling Ca-
pacitor, leakage current of the VSP3200 and VSP3210 input
circuitry, and the time period of CK1.
Figure 2 shows the equivalent circuit of the VSP3200 and
VSP3210 inputs.
In this equivalent circuit, Input Coupling Capacitor C
IN
, and
Sampling Capacitor C
1
, are constructed as a capacitor divider
during CK1. For AC analysis, OP inputs are grounded.
Therefore, the sampling voltage, V
S
, during CK1 is:
V
S
= (C
IN
/(C
IN
+ C
1
)) • V
IN
From the above equation, we know that a larger C
IN
makes
V
S
close to V
IN
. In other words, the input signal (V
IN
) will
not be attenuated if C
IN
is large.
However, there is a disadvantage of using a large C
IN
: it will
take longer for the CLP signal to charge up C
IN
so that the
input circuitry of the VSP3200 and VSP3210 can work
properly.
CHOOSING C
MAX
AND C
MIN
As mentioned before, a large C
IN
is better if there is enough
time for the CLP signal to charge up C
IN
so that the input
circuitry of the VSP3200 and VSP3210 can work properly.
Typically, 0.01µF to 0.1µF of C
IN
can be used for most
cases.
In order to optimize C
IN
, the following two equations can be
used to calculate the maximum (C
MAX
) and minimum (C
MIN
)
values of C
IN
:
C
MAX
= (t
CK1
• N)/[R
SW
• ln(V
D
/V
ERROR
)]
where t
CK1
is the time when both CK1 and CLP go HIGH,
and N is the number of black pixels; R
SW
is the switch
resistance of the VSP3200 and VSP3210 (typically, driver
impedance + 4kW); V
D
is the droop voltage of C
IN
; V
ERROR
is the voltage difference between V
S
and V
CLAMP
.
C
MIN
= (II/V
ERROR
) • t
where II is the leakage current of the VSP3200 and VSP3210
input circuitry (10nA is a typical number for this leakage
current); t is the clamp pulse period.
SETTING FOR FULL-SCALE INPUT RANGE
The input range of the internal 16-bit A/D converter can be
set in two ways:
• Internal reference: to set the internal reference mode, D2
of the configuration register must be set to “0” and the
reference voltage set through D1. The full-scale input
voltage setting is twice the reference voltage. When the
reference voltage is set at 1V (D1 = “0”), the full-scale
voltage is 2Vp-p. However, when the reference voltage is
set at 1.5V (D1 = “1”), the full-scale voltage is 3Vp-p. In
internal reference mode, V
REF
should be connected to
GND with a 0.1µF capacitor. Do not use V
REF
voltages in
Op
Amp
C
IN
CLP
C
1
4pF
CK1
CK2
C
2
4pF
V
CLAMP
V
IN
CK1
FIGURE 2. Equivalent Circuit of VSP3200 and VSP3210
Inputs.
Not Recommended for New Designs