Datasheet

VSP3200, 3210
11
SBMS012A
The VSP3210 can be operated in Demultiplexed mode as the
digital output (B13-based Big Endian Format), as shown in
Table I. The VSP3210 outputs the high byte (upper 8 bits)
by pin 31 through pin 38 at the rising edge of ADCCK
HIGH, then outputs the low byte (lower 8 bits) by pin 31
through pin 38 at the falling edge of ADCCK (as shown in
Table II). An 8-bit interface can be used between the
VSP3200 and the Digital Signal Processor, allowing for a
low-cost system solution.
DIGITAL OUTPUTS
The digital outputs of the VSP3200 and VSP3210 are
designed to be compatible with both high-speed TTL and
CMOS logic families. The driver stage of the digital outputs
is supplied through a separate supply pin, V
DRV
(pin 41),
which is not connected to the analog supply pins (V
CC
). By
adjusting the voltage on V
DRV
, the digital output levels will
vary respectively. Thus, it is possible to operate the VSP3200
and VSP3210 on +5V analog supplies while interfacing the
digital outputs to 3V logic. It is recommended to keep the
capacitive loading on the data lines as low as possible
(typically less than 15pF). Larger capacitive loads demand-
ing higher charging current surges can feed back to the
analog portion of the VSP3200 and VSP3210 and influence
the performance. If necessary, external buffers or latches
may be used, providing the added benefit of isolating the
VSP3200 and VSP3210 from any digital noise activities on
the bus coupling back high-frequency noise. In addition,
resistors in series with each data line may help minimize the
surge current. Their use depends on the capacitive loading
seen by the converter. As the output levels change from
LOW to HIGH and HIGH to LOW, values in the range of
100W to 200W will limit the instantaneous current the output
stage has to provide for recharging the parasitic capaci-
tances.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The VSP3200 and VSP3210 have one PGA which is in-
serted between the CDSs and the 3:1 MUX. The PGA is
controlled by a 6-bit of Gain Register; each channel (Red,
Green, and Blue) has its own Gain Register.
The gain varies from 1 to 4.8 (0dB to 14dB), and the curve
has log characteristics. Gain Register Code all “0” corre-
sponds to minimum gain, and Code all “1” corresponds to
maximum gain.
The transfer function of the PGA is:
Gain = 80/(80 – GC)
where, GC is the integer representation of the 6-bit PGA
gain register.
Figure 1 shows the PGA transfer function plots.
PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
High Byte ––B15 B14 B13 B12 B11 B10 B9 B8 –– ––– –
Low Byte ––B7 B6 B5 B4 B3 B2 B1 B0 –– ––– –
TABLE II. Output Format for VSP3210.
PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
High Byte B15 B14 B13 B13 B11 B10 B9 B8 Low Low Low Low Low Low Low Low
Low Byte B7 B6 B5 B4 B3 B2 B1 B0 Low Low Low Low Low Low Low Low
TABLE I. Output Format for VSP3200 (Demultiplexed Mode).
FIGURE 1. PGA Transfer Function Plots.
PGA Gain Code (0 to 3)
Gain
5
4.5
4
3.5
3
2.5
2
1.5
1
Gain (dB)
0 4 8
12 16 20 24 28 32 36 40 44 48 52 56 60
PGA Gain Code (0 to 63)
14
12
10
8
6
4
2
0
0 4 8
12 16 20 24 28 32 36 40 44 48 52 56 60
Not Recommended for New Designs