Datasheet

VSP3200, 3210
10
SBMS012A
THEORY OF OPERATION
INTRODUCTION
The VSP3200 and VSP3210 are complete mixed-signal ICs
that contain all of the key features associated with the
processing of the CCD line sensor output signal in scanners,
photo copiers, and similar applications. See the simplified
block diagram on page 1 for details. The VSP3200 and
VSP3210 include Correlated Double Samplers (CDSs), Pro-
grammable Gain Amplifiers (PGAs), Multiplexer (MUX),
Analog-to-Digital (A/D) converter, input clamp, offset con-
trol, serial interface, timing control, and reference control
generator.
The VSP3200 and VSP3210 can be operated in one of the
following two modes:
• 1-Channel CCD mode
• 3-Channel CCD mode
1-CHANNEL CCD MODE
In this mode, the VSP3200 and VSP3210 process only one
CCD signal (D3 of the Configuration Register sets to “1”).
The CCD signal is AC-coupled to RINP, GINP, or BINP
(depending on D4 and D5 of the Configuration Register). The
CLP signal enables internal biasing circuitry to clamp this
input to a proper voltage, so that internal CDS circuitry can
work properly. The VSP3200 and VSP3210 inputs may be
applied as DC-coupled inputs, which needs to be level-shifted
to a proper DC level.
The CDS takes two samples of the incoming CCD signals:
the CCD reset signal is taken on the falling edge of CK1, and
the CCD information is taken on the falling edge of CK2.
These two samples are then subtracted by the CDS and the
result is stored as a CDS output.
In the 1-Channel CCD mode, only one of the three channels
is enabled. Each channel consists of a 10-bit offset Digital-to-
Analog Converter (DAC) with a range from –500mV to
+500mV. A 3-to-1 analog MUX is inserted between the CDSs
and a high-performance, 16-bit A/D converter. The outputs of
the CDSs are then multiplexed to the A/D converter for
digitization. The analog MUX is not cycling between channels
in this mode. Instead, it is connected to a specific channel,
depending on the contents of D4 and D5 in the Configuration
Register.
The VSP3200 allows two types of output modes:
• Normal (D7 of Configuration Register sets to “0”).
• Demultiplexed (D7 of Configuration Register sets to “1”).
The VSP3210 allows one type of output mode:
• Demultiplexed (D7 of Configuration Register sets to “1”).
As specified in the “1-Channel CCD Mode” timing diagram,
the rising edge of CK1 must be in the HIGH period of
ADCCK, and at the same time, the falling edge of the CK2
must be in the LOW period of ADCCK. Otherwise, the
VSP3200 and VSP3210 will not function properly.
3-CHANNEL CCD MODE
In the 3-Channel CCD mode, the VSP3200 and VSP3210 can
simultaneously process triple output CCD signals. CCD sig-
nals are AC coupled to the RINP, GINP, and BINP inputs. The
CLP signal enables internal biasing circuitry to clamp these
inputs to a proper voltage so that internal CDS circuitry can
work properly. The VSP3200 and VSP3210 inputs may be
applied as DC-coupled inputs, which need to be level-shifted
to a proper DC level.
The CDSs take two samples of the incoming CCD signals:
the CCD reset signals are taken on the falling edge of CK1,
and the CCD information is taken on the falling edge of
CK2. These two samples are then subtracted by the CDSs
and the results are stored as a CDS output.
In this mode, three CDSs are used to process three inputs
simultaneously. Each channel consists of a 10-bit Offset
DAC (range from –500mV to +500mV). A 3-to-1 analog
MUX is inserted between the CDSs and a high-performance,
16-bit A/D converter. The outputs of the CDSs are then
multiplexed to the A/D converter for digitization. The ana-
log MUX is switched at the falling edge of CK2, and can be
programmed to cycle between the Red, Green, and Blue
channels. When D6 of the Configuration Register sets to
“0”, the MUX sequence is Red > Green > Blue. When D6
of the Configuration Register sets to “1”, the MUX sequence
is Blue > Green > Red.
MUX resets at the falling edge of CK1. In the case of a
Red > Green > Blue sequence, it resets to “R”, and in the
case of a Blue > Green > Red sequence, it resets to “B”.
The VSP3200 allows two types of output modes:
• Normal (D7 of Configuration Register sets to “0”).
• Demultiplexed (D7 of Configuration Register sets to “1”).
The VSP3210 allows one type of output mode:
• Demultiplexed (D7 of Configuration Register sets to “1”).
As specified in the “3-Channel CCD Mode” timing diagram,
the falling edge of CK2 must be in the LOW period of
ADCCK. If the falling edge of CK2 is in the HIGH period
of ADCCK (in the timing diagram, ADCCK for sampling
B-channel), the VSP3200 and VSP3210 will not function
properly.
DIGITAL OUTPUT FORMAT
See Table I for the Digital Output Format. The VSP3200 and
VSP3210 can be operated in one of the following two digital
output modes:
• Normal output.
• Demultiplexed (B15-based Big Endian Format).
In Normal mode, the VSP3200 outputs the 16-bit data by B0
(pin 25) through B15 (pin 40) simultaneously.
In Demultiplexed mode, the VSP3200 outputs the high byte
(upper 8 bits) by B8 (pin 33) through B15 (pin 40) at the
rising edge of ADCCK HIGH, then outputs the low byte
(lower 8 bits) by B8 (pin 33) through B15 (pin 40) at the
falling edge of ADCCK.
Not Recommended for New Designs