Datasheet
4
®
VSP3100
Top View LQFP
PIN DESCRIPTIONS
PIN DESIGNATOR TYPE DESCRIPTION PIN DESIGNATOR TYPE DESCRIPTION
1 CM AO Common-Mode Voltage
2 REFP AO Top Reference
3 AGND P Analog Ground
4 INN AI Red/Green/Blue Channel Reference Input
5 RINP AI Red Channel Analog Input
6 AGND P Analog Ground
7 GINP AI Green Channel Analog Input
8 AGND P Analog Ground
9 BINP AI Blue Channel Analog Input
10 AGND P Analog Ground
11 V
CC
P Analog Power Supply, +5V
12 CLP DI Clamp Enable:
“High” = Enable, “Low” = Disable
13 V
CC
P Analog Power Supply, +5V
14 ADCCK DI Clock for A/D Converter Digital Data Output
15 CK1 DI Sample Reference Clock
16 CK2 DI Sample Data Clock
17 AGND P Analog Ground
18 RD DI Read Signal for Registers
19 WRT DI Write Signal for Registers
20 P/S DI Parallel/Serial Port Select
“High” = Parallel Port, “Low” = Serial Port
21 SD DI Serial Data Input
22 SCLK DI Serial Data Shift Clock
23 V
CC
P Analog Power Supply, +5V
24 OE DI Output Enable
PIN CONFIGURATION
25 B0 (D0) LSB DIO A/D Output (Bit 0) and Register Data (Bit 0)
26 B1 (D1) DIO A/D Output (Bit 1) and Register Data (Bit 1)
27 B2 (D2) DIO A/D Output (Bit 2) and Register Data (Bit 2)
28 B3 (D3) DIO A/D Output (Bit 3) and Register Data (Bit 3)
29 B4 (D4) DIO A/D Output (Bit 4) and Register Data (Bit 4)
30 B5 (D5) DIO A/D Output (Bit 5) and Register Data (Bit 5)
31 B6 (D6) DIO A/D Output (Bit 6) and Register Data (Bit 6)
32 B7 (D7) DIO A/D Output (Bit 7) and Register Data (Bit 7)
33 B8 (D8) DIO A/D Output (Bit 8) and Register Data (Bit 8)
B0: Demiltiplexed Mode A/D Output (Bit 0) when Demultiplexed Output Mode
34 B9 (D9) DIO A/D Output (Bit 9) and Register Data (Bit 9)
B1: Demiltiplexed Mode A/D Output (Bit 1) when Demultiplexed Output Mode
35 B10 (A0) DIO A/D Output (Bit 10) and Register Address (Bit 0)
B2: Demiltiplexed Mode A/D Output (Bit 2) when Demultiplexed Output Mode
36 B11 (A1) DIO A/D Output (Bit 11) and Register Address (Bit 1)
B3: Demiltiplexed Mode A/D Output (Bit 3) when Demultiplexed Output Mode
37 B12 (A2) DIO A/D Output (Bit 12) and Register Address (Bit 2)
B4: Demiltiplexed Mode A/D Output (Bit 4) when Demultiplexed Output Mode
38 B13 MSB DO A/D Output (Bit 13)
B5: Demiltiplexed Mode A/D Output (Bit 5) when Demultiplexed Output Mode
39 AGND P Analog Ground
40 AGND P Analog Ground
41 V
DRV
P Digital Output Driver Power Supply
42 V
CC
P Analog Power Supply, +5V
43 V
CC
P Analog Power Supply, +5V
44 AGND P Analog Ground
45 TP0 AO A/D Converter Input Monitor Pin (single-ended output)
46 V
REF
AIO Reference Voltage Input/Output
47 V
CC
P Analog Power Supply, +5V
48 REFN AO Bottom Reference
36
35
34
33
32
31
30
29
28
27
26
25
B11 (A1)
B10 (A0)
B9 (D9)
B8 (D8)
B7 (D7)
B6 (D6)
B5 (D5)
B4 (D4)
B3 (D3)
B2 (D2)
B1 (D1)
B0 (D0) LSB
REFN
V
CC
V
REF
TP0
AGND
V
CC
V
CC
V
DRV
AGND
AGND
B13 MSB
B12 (A2)
V
CC
ADCCK
CK1
CK2
AGND
RD
WRT
P/S
SD
SCLK
V
CC
OE
1
2
3
4
5
6
7
8
9
10
11
12
CM
REFP
AGND
INN
RINP
AGND
GINP
AGND
BINP
AGND
V
CC
CLP
48 47 46 45 44 43 42
41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
VSP3100Y
Not Recommended for New Designs