Datasheet

16
®
VSP3100
These registers can be accessed by the following two pro-
gramming modes:
(1) Parallel Programming Mode using digital data output
pins, with the data bus assigned as D0 to D9 (pins 25 to 34),
and the address bus as A0 to A2 (pins 35 to 37). It can be
used for both reading and writing operations. However, it
cannot be used by the Demultiplexed mode (when D7 of the
Configuration Register is set to “1”).
(2) Serial Programming Mode using a serial port, Serial Data
(SD), the Serial Shift Clock (SCLK), and Write Signal
(WRT) assigned.
It can be used only for writing operations; reading opera-
tions via the serial port are prohibited.
Table III shows how to access these modes.
Power-on default value is all “0s”, set to 3-channel CCD
mode with 1V internal reference, R > G > B MUX sequence,
and normal output mode.
For reading/writing to the Configuration Register, the ad-
dress will be A2 = “0”, A1 =“0”, and A0 = “0”.
For Example:
A 3-channel CCD with internal reference V
REF
= 1V (2V
full-scale input), R > G > B sequence and normal output
mode will be D0 = “0”, D1 = “0”, D2 =“0”, D3 = “0”,
D4 = “x (don’t care)”, D5 = “x (don’t care)”, D6 = “0”, and
D7 = “0”.
For this example, bypass V
REF
with an appropriate capacitor
(for example, 10µF to 0.1µF) when internal reference mode
is used.
Another Example:
A 1-channel CIS mode (Green channel) with an external
1.2V reference (2.4V full-scale input), Demultiplexed Out-
put mode will be D0 = “1”, D1 = “x (don’t care)”, D2 = “1”,
D3 = “1”, D4 = “0”, D5 = “1”, D6 = “x (don’t care)”, and
D7 = “1”.
For this example, V
REF
will be an input pin applied with
1.2V.
OFFSET REGISTER
Offset Registers control the analog offset input to channels
prior to the PGA. There is a 10-bit Offset Register on each
channel. The offset range varies from –400mV to +400mV.
The Offset Register uses a straight binary code. All “0s”
corresponds to –400mV, and all “1s” corresponds to +400mV
of the offset adjustment. The register code 200
H
corresponds
to 0mV of the offset adjustment. The Power-on default value
of the Offset Register is all ”0s”, so the offset adjustment
should be set to –400mV.
PGA GAIN REGISTER
PGA Gain Registers control the gain to channels prior to the
digitization by the A/D converter. There is a 5-bit PGA Gain
Register on each channel. The gain range varies from 1 to
4.44 (from 0dB to 13dB). The PGA Gain Register is a
straight binary code. All “0s” corresponds to an analog gain
of 0dB, and all “1s” corresponds to an analog gain of 13dB.
PGA Transfer function is log gain curve. Power-on default
value is all “0s”, so that it sets the gain of 0dB.
BIT LOGIC ‘0’ LOGIC ‘1’
D0 CCD mode CIS mode
D1 V
REF
= 1V V
REF
=1.5V
D2 Internal Reference External Reference
D3 3-channel Mode, 1-channel Mode,
D4 and D5 disabled D4 and D5 enabled
D4,D5 (disabled when 3-channel) D4 D5
00
1-channel mode, Red channel
01 1-channel mode, Green channel
10 1-channel mode, Blue channel
D6 MUX Sequence MUX Sequence
Red > Green > Blue Blue > Green >Red
D7 Normal output mode Demultiplexed output mode
TABLE IV. Configuration Register Design.
OE P/S MODE
0 0 Digital data output enabled, Serial mode enabled
0 1 Prohibit mode
1 0 Digital data output disabled, Serial mode enabled
1 1 Digital data output disabled, Parallel mode enabled
TABLE III. Access Mode for Serial and Parallel Port.
CONFIGURATION REGISTER
The Configuration Register design is shown in Table IV.
Not Recommended for New Designs