Datasheet

15
®
VSP3100
There are many factors that decide what size of Input
Coupling Capacitor is needed. Those factors are CCD signal
swing, voltage difference between the Input Coupling Ca-
pacitor, leakage current of the VSP3100 input circuitry, and
the time period of CK1.
Figure 2 shows the equivalent circuit of the VSP3100 inputs.
CHOOSE C
MAX
AND C
MIN
As mentioned, a large C
IN
is better if there is enough time for
the CLP signal to charge up C
IN
so that the input circuitry of
the VSP3100 can work properly. Typically, 0.01µF to 0.1µF
of C
IN
can be used for most cases.
In order to optimize C
IN
, the following two equations can be
used to calculate the maximum (C
MAX
) and minimum (C
MIN
)
values of C
IN
:
C
MAX
= (t
CK1
• N)/[R
SW
• ln(V
D
/V
ERROR
)]
where t
CK1
is the time when both CK1 and CLP go HIGH,
and N is the number of black pixels; R
SW
is the switch
resistance of the VSP3100 (typically, driver impedance +
4kΩ); V
D
is the droop voltage of C
IN
; V
ERROR
is the voltage
difference between V
S
and V
CLAMP
.
C
MIN
= (I/V
ERROR
) • t
where I is the leakage current of the VSP3100 input circuitry
(10nA is a typical number for this leakage current);
t is the clamp pulse period.
PROGRAMMING VSP3100
The VSP3100 consists of 3 CCD/CIS channels and a 14-bit
A/D. Each channel (Red, Green, and Blue) has its own
10-bit Offset and 5-bit Gain Adjustable Registers to be
programmed by the user. There is also an 8-bit Configura-
tion Register, on-chip, to program the different operation
modes. Those registers are shown in Table II.
In this equivalent circuit, Input Coupling Capacitor C
IN
, and
Sampling Capacitor C
1
, are constructed as a capacitor divider
(during CK1). For AC analysis, OP inputs are grounded.
Therefore, the sampling voltage, V
S
, (during CK1) is:
V
S
= (C
IN
/(C
IN
+ C
1
)) • V
IN
From the above equation, we know that a larger C
IN
makes
V
S
close to V
IN
. In other words, input signal, V
IN
, will not be
attenuated if C
IN
is large.
However, there is a disadvantage of using a large C
IN
. It will
take longer for the CLP signal to charge up C
IN
so that the
input circuitry of the VSP3100 can work properly.
OP
AMP
C
IN
CLP
C
1
4pF
CK1
CK2
C
2
4pF
V
CLAMP
V
IN
CK1
FIGURE 2. Equivalent Circuit of VSP3100 Inputs.
TABLE II. On-Chip Registers.
ADDRESS POWER-ON
A2 A1 A0 REGISTER DEFAULT VALUE
0 0 0 Configuration Register (8-bit) All “0s”
0 0 1 Red Channel Offset Register (10-bit) All “0s”
0 1 0 Green Channel Offset Register (10-bit) All “0s”
0 1 1 Blue Channel Offset Register (10-bit) All “0s”
1 0 0 Red Channel Gain Register (5-bit) All “0s”
1 0 1 Green Channel Gain Register (5-bit) All “0s”
1 1 0 Blue Channel Gain Register (5-bit) All “0s”
1 1 1 Reserved
Not Recommended for New Designs