Datasheet

12
®
VSP3100
THEORY OF OPERATION
VSP3100 can be operated in one of the following four
modes:
(1) 1-Channel CCD
(2) 1-Channel CIS
(3) 3-Channel CCD
(4) 3-Channel CIS
1-CHANNEL CCD MODE
In this mode, the VSP3100 processes only one CCD signal
(D3 of the Configuration Register sets to “1”). The CCD
signal is AC-coupled to RINP, GINP, or BINP (depending
on D4, D5 of the Configuration Register). The CLP signal
enables internal biasing circuitry to clamp this input to a
proper voltage, so that internal CDS circuitry can work
properly. The VSP3100 input may be applied as a DC-
coupled input, which needs to be level-shifted to a proper
DC level.
The CDS takes two samples of the incoming CCD signals.
The CCD reset signal is taken on the falling edge of CK1 and
the CCD information is taken on the falling edge of CK2.
These two samples are then subtracted by the CDS and the
result is stored as a CDS output.
In this mode, only one of the three channels is enabled. Each
channel consists of a 10-bit Offset DAC (range from
–400mV to +400mV). A 3-to-1 analog MUX is inserted
between the CDSs and a high-performance 14-bit analog-to-
digital converter. The outputs of the CDSs are then multi-
plexed to the A/D converter for digitization. The analog
MUX is not cycling between channels in this mode. Instead,
it is connected to a specific channel, depending on the
contents of D4 and D5 in the Configuration Register.
The VSP3100 allows two types of output modes:
1) Normal (D7 of Configuration Register sets to “0”).
2) Demultiplexed (D7 of Configuration Register sets to “1”).
As specified in the “1-Channel CCD Mode” timing diagram,
the rising edge of CK1 must be in the HIGH period of
ADCCK, and at the same time, the falling edge of the CK2
must be in the LOW period of ADCCK. Otherwise, the
VSP3100 will not function properly.
1-CHANNEL CIS MODE
In this mode, the VSP3100 operates as a 1-channel sampler
and digitizer. Unlike CDS modes, the VSP3100 takes only
one sample on the falling edge of the CK1. Since only one
sample is taken, CK2 is grounded in this operation. The
input signal is DC coupled in most cases. Here, VSP3100
inputs are differential input. Using the Red channel as an
example, RINP is the CIS input signal, and INN is the CIS
common reference signal input. The same applies to the
Green channel (GINP and INN) and Blue channel (BINP
and INN).
In this mode, CDS becomes CIS (act like sample-and-hold).
Each channel consists of a 10-bit Offset DAC (range from
–400mV to +400mV).
A 3-to-1 analog MUX is inserted between the CISs and a
high-performance, 14-bit A/D converter. The outputs of the
CIS are then multiplexed to the A/D converter for digitiza-
tion. The analog MUX is not cycling between channels in
this mode. Instead, the analog MUX is connected to a
specific channel, depending on the contents of D4 and D5 in
the Configuration Register.
The VSP3100 allows two types of output modes:
1) Normal (D7 of Configuration Register sets to “0”).
2) Demultiplexed (D7 of Configuration Register sets to “1”).
As specified in the “1-Channel CIS Mode” timing diagram,
the active period of both CK1 (t
CK1B
) and CK2 (t
CK2B
) must
be in the LOW period of ADCCK. If it is in the HIGH period
of ADCCK, the VSP3100 will not function properly.
3-CHANNEL CCD MODE
In this mode, the VSP3100 can simultaneously process triple
output CCD signals. CCD signals are AC coupled to the
RINP, GINP, and BINP inputs. The CLP signal enables
internal biasing circuitry to clamp these inputs to a proper
voltage so that internal CDS circuitry can work properly.
VSP3100 inputs may be applied as a DC-coupled inputs,
which need to be level-shifted to a proper DC level.
The CDSs take two samples of the incoming CCD signals.
The CCD reset signals are taken on the falling edge of CK1
and the CCD information is taken on the falling edge of
CK2. These two samples are then subtracted by the CDSs
and the results are stored as a CDS output.
Not Recommended for New Designs