Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Video editing CCD signal processor (14-bit) LQFP 48 (7x7)

14-Bit, 10MHz

CCD/CIS SIGNAL PROCESSOR

VSP3100

DESCRIPTION

The VSP3100 is a complete CCD/CIS image proces-

sor which operates from a single +5V supply.

This complete image processor includes three Corre-

lated Double Samplers (CDS) and Programmable Gain

Amplifiers (PGA) to process CCD signals.

These three channel inputs also allow Contact Image

Sensor (CIS) inputs.

The VSP3100 is an interface compatible with the

VSP3000 which is 12-bit one-chip product.

The VSP3100 can be operated from 0°C to +85°C and

is available in an LQFP-48 package.

FEATURES

● INTEGRATED TRIPLE-CORRELATED

DOUBLE SAMPLER

● OPERATION MODE SELECTABLE:

1-Channel, 3-Channel, 10MSPS (typ),

CCD/CIS Mode

● PROGRAMMABLE GAIN AMPLIFIER:

0dB to +13dB

● SELECTABLE OUTPUT MODES:

Normal/Demultiplexed

● OFFSET CONTROL RANGE: ±400mV

● +3V, +5V Digital Output

● LOW POWER: 450mW (typ)

● LQFP-48 SURFACE-MOUNT PACKAGE

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

For most current data sheet and other product

information, visit www.burr-brown.com

RINP

INN

Clamp

GINP

Clamp

CDS

PGA

BINP

Clamp

10-Bit

DAC

10-Bit

DAC

10-Bit

DAC

MUX

Timing Generator

Reference

Circuit

Digital

Output

Control

Offset

Gain

Control

Configuration

Port

14-Bit

A/D

P/S

WRT

SCLK

REFP

REFN

DRV

B0-B13

(A0-A2, D0-D9)

VSP3100

CK1CLP CK2

ADCCK

REF

TP0

VSP3100

SBMS007

Not Recommended for New Designs

Summary of content (23 pages)

PAGE 1
Not Recommended for New Designs VSP3100 ® VSP 310 0 For most current data sheet and other product information, visit www.burr-brown.
PAGE 2
Not Recommended for New Designs SPECIFICATIONS At TA = full specified temperature range, VCC = +5V, fADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, PGA gain = 1, normal output mode, no output load, unless otherwise specified.
PAGE 3
Not Recommended for New Designs ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage(2) .............................................................................................................. +6.5V Supply Voltage Differences(3) ................................................................................... ±0.1V GND Voltage Differences(4) ........................................................................................ ±0.1V Digital Input Voltage ...............
PAGE 4
Not Recommended for New Designs PIN CONFIGURATION VCC VREF TP0 AGND VCC VCC VDRV AGND AGND B13 MSB B12 (A2) LQFP REFN Top View 48 47 46 45 44 43 42 41 40 39 38 37 CM 1 36 B11 (A1) REFP 2 35 B10 (A0) AGND 3 34 B9 (D9) INN 4 33 B8 (D8) RINP 5 32 B7 (D7) AGND 6 31 B6 (D6) VSP3100Y VCC 11 26 B1 (D1) CLP 12 25 B0 (D0) LSB 16 17 18 19 20 21 22 23 24 OE 15 WRT 14 VCC 27 B2 (D2) SCLK AGND 10 SD 28 B3 (D3) 13 30 B5 (D5) P/S 9 RD BINP AGND 29 B
PAGE 5
Not Recommended for New Designs TIMING DIAGRAMS Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted.
PAGE 6
Not Recommended for New Designs TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted.
PAGE 7
Not Recommended for New Designs TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted.
PAGE 8
Not Recommended for New Designs TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted.
PAGE 9
Not Recommended for New Designs TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted.
PAGE 10
Not Recommended for New Designs TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted.
PAGE 11
Not Recommended for New Designs TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V supply, tADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, PGA Gain = 1, normal output mode, no load, unless otherwise specified. PGA TRANSFER FUNCITON SAMPLE QUALITY, N = 100 POWER DISSIPATION vs POWER SUPPLY 1 CH MODE 5.0 500 4.5 450 Power Dissipation (mW) 4.0 3.5 2.5 2.0 1.5 1.0 400 350 300 250 0.5 0 200 0 5 10 15 20 PGA Gain Setting 25 30 35 4.7 5 Power Supply Voltage (V) 5.
PAGE 12
Not Recommended for New Designs THEORY OF OPERATION 1-CHANNEL CIS MODE In this mode, the VSP3100 operates as a 1-channel sampler and digitizer. Unlike CDS modes, the VSP3100 takes only one sample on the falling edge of the CK1. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC coupled in most cases. Here, VSP3100 inputs are differential input. Using the Red channel as an example, RINP is the CIS input signal, and INN is the CIS common reference signal input.
PAGE 13
Not Recommended for New Designs In this mode, three CDSs are used to process three inputs simultaneously. Each channel consists of a 10-bit Offset DAC (range from –400mV to +400mV). A 3-to-1 analog MUX is inserted between the CDSs and a high-performance, 14-bit A/D converter. The outputs of the CDSs are then multiplexed to the A/D converter for digitization. The analog MUX is switched at the falling edge of CK2, and can be programmed to cycle between the Red, Green, and Blue channels.
PAGE 14
Not Recommended for New Designs DIGITAL OUTPUTS The transfer function of the PGA is: The digital outputs of the VSP3100 are designed to be compatible with both high-speed TTL and CMOS logic families. The driver stage of the digital outputs is supplied through a separate supply pin, VDRV (pin 41), which is not connected to the analog supply pins (VCC). By adjusting the voltage on VDRV, the digital output levels will vary respectively.
PAGE 15
Not Recommended for New Designs CHOOSE CMAX AND CMIN There are many factors that decide what size of Input Coupling Capacitor is needed. Those factors are CCD signal swing, voltage difference between the Input Coupling Capacitor, leakage current of the VSP3100 input circuitry, and the time period of CK1. Figure 2 shows the equivalent circuit of the VSP3100 inputs.
PAGE 16
Not Recommended for New Designs These registers can be accessed by the following two programming modes: Power-on default value is all “0s”, set to 3-channel CCD mode with 1V internal reference, R > G > B MUX sequence, and normal output mode. (1) Parallel Programming Mode using digital data output pins, with the data bus assigned as D0 to D9 (pins 25 to 34), and the address bus as A0 to A2 (pins 35 to 37). It can be used for both reading and writing operations.
PAGE 17
Not Recommended for New Designs OFFSET AND GAIN CALIBRATION SEQUENCE RECOMMENDATION FOR POWER SUPPLY AND GROUNDING Proper grounding, bypassing, short lead length, and the use of ground planes are particularly important for high-frequency designs. Multi-layer PC boards are recommended for the best performance since they offer distinct advantages such as minimization of ground impedance, separation of signal layers by ground layers, etc.
PAGE 18
Not Recommended for New Designs FIGURE 3. Demo Board Schematic (DEM-VSP3100).
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device VSP3100Y/2K Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 9.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.5 2.0 12.0 16.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VSP3100Y/2K LQFP PT 48 2000 367.0 367.0 38.
PAGE 23
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.