Datasheet

t
WP
CCD N N+1 N+2 N+3
t
PD
t
WD
t
WD
t
S
t
S
t
CKP
t
ADC
t
ADC
t
INHIBIT1
t
INHIBIT2
t
OD
SHP
SHD
ADCCK
B0-B9 N 6- N 5- N 4- N 3-
Not Recommended for New Designs
VSP2582
www.ti.com SBES002B –JUNE 2008–REVISED JUNE 2011
TIMING SPECIFICATIONS
Figure 1. TG High-Speed Pulse Specifications
TIMING CHARACTERISTICS (36-MHz Operation)
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CKP
Clock period 27.7 ns
t
ADC
ADCCK high or low level 6.5 13.8 21.2 ns
t
WP
SHP pulse width 5.9 6.9 ns
t
WD
SHD pulse width 5.9 6.9 ns
t
PD
SHP trailing edge to SHD leading edge 5.0 6.9 ns
t
DP
SHD trailing edge to SHP leading edge 5.2 6.9 ns
t
S
Sampling delay 3 ns
Inhibited clock period 1 (from rising edge of SHP to rising
t
INHIBIT1
–9 13 ns
edge of ADCCK)
Inhibited clock period 2 (from rising edge of SHD to rising
t
INHIBIT2
–8 –0 ns
edge of ADCCK)
t
OD
Output delay 0 5 ns
DL Data latency 6 Clocks
TIMING CHARACTERISTICS (27-MHz Operation)
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CKP
Clock period 37 ns
t
ADC
ADCCK high or low level 6.5 18.5 30.5 ns
t
WP
SHP pulse width 5.9 6.9 ns
t
WD
SHD pulse width 5.9 6.9 ns
t
PD
SHP trailing edge to SHD leading edge 5.9 6.9 ns
t
DP
SHD trailing edge to SHP leading edge 5.2 6.9 ns
t
S
Sampling delay 3 ns
Inhibited clock period 1 (from rising edge of SHP to rising
t
INHIBIT1
–9 13 ns
edge of ADCCK)
Inhibited clock period 2 (from rising edge of SHD to rising
t
INHIBIT2
–8 –0 ns
edge of ADCCK)
t
OD
Output delay 0 5 ns
DL Data latency 6 Clocks
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: VSP2582