Datasheet

Clamp
CDS
16-Bit
Analog-to-Digital
Converter
DPGA
and
OutputRegister
Internal
Timing
Circuit
SerialInterface
and
Register
Digital
Output
12-Bit
DecoderCDSBuff
InternalReference
SHP/SHD ADCCK
ADCCK
CLPDM
GainSetting
BYP REFPBYPP COP REFN
CCDIN
CCD
Output
Signal
SHP
SHD
CLPDM
CLPOB
SDATA
SCLK
SLOAD
Not Recommended for New Designs
VSP2582
SBES002B –JUNE 2008–REVISED JUNE 2011 www.ti.com
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME NO. TYPE
(1)
DESCRIPTION
AGND 22 P Analog ground
AGND 23 P Analog ground
CCDIN 24 AI CCD signal input
BYP 25 AO Internal reference bypass to ground by 0.1 μF
BYPP 26 AO Internal reference bypass to ground by 1000 pF
COB 27 AO OB loop feed back capacitor
REFN 28 AO Internal reference bypass to ground by 0.1 μF
REFP 29 AO Internal reference bypass to ground by 0.1 μF
V
CC
30 P Analog power supply
AGND 31 P Analog ground
SLOAD 32 DI Serial data latch signal
SDATA 33 DI Serial data input
SCLK 34 DI Serial data clock
B0 35 DO Data out bit 0 (LSB)
B1 36 DO Data out bit 1
FUNCTIONAL BLOCK DIAGRAM
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