Datasheet

Not Recommended for New Designs
VSP2582
www.ti.com SBES002B –JUNE 2008–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted).
VSP2582RHN
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Conversion rate 36 MHz
ANALOG INPUT (CCDIN)
Input signal level for full-scale out CDS gain = 0 dB, DPGA gain = 0 dB 1000 mV
Maximum input range CDS gain = –3 dB, DPGA gain = 0 dB 1300 mV
Input capacitance 15 pF
Input limit –0.3 3.3 V
TRANSFER CHARACTERISTICS
Differential nonlinearity (DNL) CDS gain = 0 dB, DPGA gain = 0 dB ±0.5 LSB
Integral nonlinearity (INL) CDS gain = 0 dB, DPGA gain = 0 dB ±2 LSB
No missing codes Ensured
Step response settling time Full-scale step input 1 Pixel
Overload recovery time Step input from 1.8 V to 0 V 2 Pixels
Data latency 6 Clock
Grounded input cap, PGA gain = 0 dB 78 dB
Signal-to-noise ratio
(1)
Grounded input cap, CDS gain = +9 dB 71 dB
CCD offset correction range –200 200 mV
INPUT CLAMP
Clamp-on resistance 400 Ω
Clamp level 1.5 V
PROGRAMMABLE ANALOG FRONT GAIN (CDS)
Minimum gain Gain code = 111 –3 dB
Default gain Gain code = 000 0 dB
Medium gain 1 Gain code = 001 3 dB
Medium gain 2 Gain code = 010 6 dB
Maximum gain Gain code = 011 9 dB
Gain control error 0.5 dB
PROGRAMMABLE DIGITAL GAIN (DPGA)
Programmable gain range –6 26 dB
Gain step 0.03125 dB
OPTICAL BLACK CLAMP LOOP
Control DAC resolution 10 Bits
Loop time constant OB loop IDAC × 1, C
COB
= 0.1 μF 40.7 μs
Programmable range of clamp level 64 312 LSB
Optical black clamp level OBCLP level at CODE = 0 1000 128 LSB
OB level program step 8 LSB
(1) Input-referred; SNR = 20 log (full-scale voltage/rms noise).
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