Datasheet

Not Recommended for New Designs

VSP2582

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SBES002B –JUNE 2008–REVISED JUNE 2011

D-PGA Register (Address: h006 and h007)

D-PGA_U D-PGA_L ANALOG GAIN DEFAULT

Digital PGA gain is givens following equation.

Gain (dB) = (D-PGA • 0.03125 ) – 6

D[3:0] D[5:0] Where: D-PGA is decimal value of 10-bit data D-PGA = 00 1100 000 = 0 dB

which is combined D-PGA_U and D-PGA_L. D-

PGA_U is MSB side of D-PGA.

A-PGA Register (Address: h008)

CDS Gain control

D2 D1 D0 ANALOG GAIN

0 0 0 0 dB (default)

0 0 1 3 dB

0 1 0 6 dB

0 1 1 9 dB

1 1 1 –3 dB

NOTE

Other values of D[2:0] are not applicable.

Power Register (Address: h009)

DATA BIT NAME DESCRIPTION DEFAULT

D[1:0] OB loop IDAC output current 00: x1, 01: x2, 10: x4, 11: x8 00

D[2] CDS Power Trim 0: Normal CDS Power, 1: Reduce CDS Power 0

D[3] ADC Power Trim 0: Normal ADC Power, 1: Reduce ADC Power 0

D[4] Ref Power Trim 0: Normal Ref Power, 1: Reduce Ref Power 0

POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS

The VSP2582 incorporates a high-precision, high-speed analog-to-digital converter and analog circuitry that is

vulnerable to any extraneous noise from the rails or elsewhere. For this reason, although the VSP2582 has

multiple supply pins, it should be treated as an analog component; all supply pins except for V

should be

because digital power lines often carry high levels of wideband noise that would otherwise be coupled into the

device and degrade achievable performance.

Proper grounding, short lead length, and proper use of ground planes are also very important for high-frequency

designs. Multilayer printed circuit boards (PCBs) are recommended for best performance because they offer

distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. It is

highly recommended that the analog and digital ground pins of the VSP2582 be joined together at the IC and be

connected only to the analog ground of the system. The driver stage of the digital outputs (B(9:0]) is supplied

through a dedicated supply pin (V

) and should be separated from the other supply pins completely, or at least

with a ferrite bead. It is also recommended to keep the capacitive loading on the output data lines as low as

possible (typically less than 15 pF). Larger capacitive loads demand higher charging current as a result of surges

that can feed back into the analog portion of the VSP2582 and affect performance. If possible, external buffers or

latches should be used that provide the added benefit of isolating the VSP2582 from any digital noise activities

on the data lines. In addition, resistors in series with each data line may help minimize surge current.

Product Folder Links: VSP2582