Datasheet

Not Recommended for New Designs
VSP2582
SBES002B –JUNE 2008–REVISED JUNE 2011 www.ti.com
Clk-Pol-ctrl Register (Address: h000)
Clk-Pol-ctrl selects the active polarity of CLPDM, CLPOB, and SHP/SHD.
DATA BIT NAME DESCRIPTION DEFAULT
D3 CLPDM Polarity 0 : Active Low 1 : Active High 0
D4 CLPOB Polarity 0 : Active Low 1 : Active High 0
D5 SHP/SHD Polarity 0 : Active Low 1 : Active High 0
AFE-ctrl(1) Register (Address: h001)
DATA BIT NAME DESCRIPTION DEFAULT
D0 Standby 0: Normal operation 1: standby 0
D3 Test enable 0: disable 1: enable 0
AFE-ctrl(2) Register (Address: h002)
AFE-ctrl(2) register controls the following data output settings.
DATA BIT NAME DESCRIPTION DEFAULT
D[1:0] Data output delay 00: 0 ns, 01: 2 ns, 10: 4 ns, 11: 6 ns 0
D4 Output enable 0: enable 1: Hi-Z 0
S-delay Register (Address: h003)
S-delay register controls SHD sampling start time from the rising edge or SHP.
DATA BIT NAME DESCRIPTION DEFAULT
D[1:0] Sampling delay for SHD 00: 0 ns, 01: 2 ns (10, 11 are not allowed) 0
Clamp Register (Address: h004)
D4 D3 D2 D1 D0 CLAMP LEVEL (VSP2582)
0 0 0 0 0 64 LSB
0 0 0 0 1 72 LSB
: :
0 0 1 1 1 120 LSB
0 1 0 0 0 128 LSB (default)
0 1 0 0 1 136 LSB
: :
1 1 1 1 0 304 LSB
1 1 1 1 1 312 LSB
Hot-pixel Register (Address: h005)
DATA BIT NAME DESCRIPTION DEFAULT
Hot pixel rejection level is givens following
equation.
D[4:0] Hot pixel rejection level 11111
R
L
(LSB) = 16 • (d[4:0] + 1)
Where: R
L
is level difference from OB level.
D5 Hot pixel rejection disable 0: disable 1: enable 1
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