Datasheet

SDATA A0 A9 D0 D5 D0 D5 D0 D5
SCLK
SLOAD
10-Bit
Address
6-Bit
Data(1)
6-Bit
Data(2)
6-Bit
Data(3)
Not Recommended for New Designs
VSP2582
www.ti.com SBES002B –JUNE 2008–REVISED JUNE 2011
SERIAL INTERFACE
All functions and settings of the VSP2582 are controlled through the serial interface. The VSP2582 serial
interface is composed of three signals: SDATA, SCLK, and SLOAD. SDATA data are sequentially stored to shift
into the register at a rising edge or SCLK, and shift register data are stored in a parallel latch at an SLOAD rising
edge. Before a write operation, SLOAD must go LOW and stay low during the write process. (Refer serial
interface timing description)
The serial interface command is composed of a 10-bit address and 6 bits of data. The fundamental write
operation is done in a 2-byte write mode. In this mode, one serial interface command is sent by one combination
of address and data bits. The 10 address bits should be sent LSB first, followed by 6 bits of data also sent LSB
first. The 6-bit command data are stored to the respective register by the 10 address bits at the rising edge of
SLOAD. The stored serial command data takes effect immediately upon the rising edge of SLOAD.
The VSP2582 also supports a continuous write mode as below. When the input serial data are longer than 2
bytes (16 bits), the following data stream is automatically recognized as the data of next address. In this mode, 6
bits of serial command data are stored to the respective register immediately when those data are fetched.
Address and data should be sent LSB first, the same as the 2-byte writing mode. If a data bit is not complete, or
if there are 6 bits at the end part of this data stream, non fill-up data bits are ignored.
The setting for the serial interface register is described in the Serial Interface Register Description. Figure 9
shows the continuous writing mode.
Figure 9. Continuous Writing Mode
Serial Interface Register Description
Table 3 shows the serial interface command data format. Descriptions of each register follow.
Table 3. Serial Interface Command Data Format
ADDRESS DATA
MSB LSB MSB LSB
REGISTERS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D5 D4 D3 D2 D1 D0
Clk-Pol-ctrl 0 0 0 0 0 0 0 0 0 0 D5 D4 D3 0 0 0
AFE-ctrl(1) 0 0 0 0 0 0 0 0 0 1 0 0 D3 0 0 D0
AFE-ctrl(2) 0 0 0 0 0 0 0 0 1 0 0 D4 0 0 D1 D0
S-delay 0 0 0 0 0 0 0 0 1 1 0 0 0 0 D1 D0
Clamp 0 0 0 0 0 0 0 1 0 0 0 D4 D3 D2 D1 D0
Hot-pixel 0 0 0 0 0 0 0 1 0 1 D5 D4 D3 D2 D1 D0
D-PGA_L 0 0 0 0 0 0 0 1 1 0 D5 D4 D3 D2 D1 D0
D-PGA_U 0 0 0 0 0 0 0 1 1 1 0 0 D3 D2 D1 D0
A-PGA 0 0 0 0 0 0 1 0 0 0 0 0 0 D2 D1 D0
Power 0 0 0 0 0 0 1 0 0 1 0 D4 D3 D2 D1 D0
Reserved Other address is reserved. Do not use
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