Datasheet

128 256

10240

InputCodeforGainControl(0to1023)

-5

-10

Gain(dB)

384 512 640 768 896

Not Recommended for New Designs

VSP2582

www.ti.com

SBES002B –JUNE 2008–REVISED JUNE 2011

Programmable Gain

The VSP2582 has a wide programmable gain range of –9 dB to 35 dB. The desired gain is set as a combination

of the CDS gain and Digital Programmable Gain Amplifier (DPGA). The CDS gain can be programmed over the

range of –3 dB to 9 dB in 3-dB steps. Digital gain can be programmed from –6 dB to 26 dB by a 0.03125 dB

step. Both gain settings are controlled through the serial interface. Digital Gain changes linearly in proportion to

the setting code. Figure 7 shows the relationship of input code and digital gain.

The recommend usage of the CDS and digital gain combination is to first adjust the CDS gain as a primary

image signal amplification; then, use digital gain as an adaptive gain control. The wide range of Digital gain

covers the necessary gain range on most applications; if necessary, the CDS gain should be changed at periods

that do not affect a picture such as a blanking period.

Figure 7. Setting Code vs. Digital Gain

Standby Mode and Power Trim Function

For the purposes of power saving, the VSP2582 can be put into a Standby Mode by the serial interface control

when the device is not in use. In this mode, all functional blocks are disabled and the digital outputs all go to

zero. Current consumption drops to approximately 2 mA. Only 10 ms are required to restore activity from the

Standby Mode. Enter and resume from the Standby Mode through the serial interface.

The VSP2582 also provides a power trim function. This function trims the power of the CDS, ADC and Reference

source. Through this trim function, power consumption can be reduced, although this reduction is not

recommended at 36-MHz operation because accuracy may degrade. This function is useful for low sampling rate

operation.

Timings

The CDS and the ADC are operated by SHP and SHD; the respective derivative timing clocks are generated by

the on-chip timing generator. The Output Register and Decoder are operated by ADCCK. The digital output data

are synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and the

output data is shown in Figure 1. CLPOB activates the black level clamp loop during the OB pixel interval and

CLPDM activates the input clamping during the dummy pixel interval. In the Standby mode, all of ADCCK, SHP,

SHD, CLPOB and CLPDM data are internally masked and pulled HIGH.

As explained in the Input Clamp and Optical Black Level (OB) Loop and OB Clamp Level sections, CLPOB is

used to control the OB loop which compensates CCD offset automatically. CLPDM is used to charge the input

clamp voltage to capacitor C

which is connected to CCDIN. For proper operation, both CLPOB and CLPDM

should be activated in the following manner.

Product Folder Links: VSP2582