Datasheet

Current

DAC

CPLOB

COB

DPGA

OBClamp

Level

DATA

OUT

16-Bit

ADC

CDS

CCDIN

BYPP

Decoder

Not Recommended for New Designs

VSP2582

www.ti.com

SBES002B –JUNE 2008–REVISED JUNE 2011

Input Clamp

The buffered CCD output is capacitively coupled to the VSP2582. The purpose of the input clamp is to restore

the dc component of the input signal that was lost with ac coupling and establish the desired dc bias point for the

CDS. Figure 5 also shows the block diagram of the input clamp. The input level is clamped to the internal

reference voltage REFP (1.5 V) during the dummy pixel interval. More specifically, the clamping function

becomes active when both CLPDM and SHP are active. Immediately after power ON, the clamp voltage of input

capacitor has not charged. The VSP2582 provides a boost-up circuit for fast charging of the clamp voltage.

16-Bit A/D Converter

The VSP2582 includes a high-speed, 16-bit ADC. This ADC uses a fully differential pipelined architecture with

correction. The ADC architecture correction is very advantageous to achieve better linearity for a smaller signal

level because large linearity errors tend to occur at specific points in the full scale; linearity improves for a level of

signal below that specific point. The ADC ensures 16-bit resolution across the entire full-scale range.

Optical Black (OB) Level Loop and OB Clamp Level

The VSP2582 has a built-in OB offset self calibration circuit (OB loop) that compensates the OB level by using

Optical Black (OB) pixels output from the CCD image sensor. A block diagram of the OB loop and the OB clamp

circuit is shown in Figure 6. The CCD offset is compensated by this calibration circuit while activating CLPOB

during a period when OB pixels are output from the CCD.

Figure 6. OB Loop and OB Level Clamp

Product Folder Links: VSP2582