Datasheet

C
INP
C
1
C
2
REFP
CCDIN
SHP/SHD
SHD
SHD
SHP
CCD
Output
SHP
CLPDM
Clamp
CDS
16-Bit
ADC
Decorder
FromSerialInterface
Current
DAC
GainControl
Buff
InternalClocks(SHP/SHDADCCK,CLPOB,CLPDM)
BYPP COP
CCDIN
DPGA
Digital
Output
12-Bit
FromInternal
TimingCircuit
Not Recommended for New Designs
VSP2582
SBES002B –JUNE 2008–REVISED JUNE 2011 www.ti.com
APPLICATION INFORMATION
Overview
The VSP2582 is a complete mixed-signal IC that contains all of the key features associated with processing the
CCD imager output signal in a video camera, digital still camera, security camera, or similar application. A
simplified block diagram is shown in Figure 4. The VSP2582 includes a correlated double sampler (CDS), a
programmable gain amplifier (PGA), an analog-to-digital converter (ADC), an input clamp, an optical black (OB)
level clamp loop, a serial interface, timing control, and a reference voltage generator. All functions and
parameters such as PGA gain control, operating mode, and other settings are controlled by the serial interface.
Figure 4. Simplified Block Diagram of VSP2582
Correlated Double Sampler (CDS)
The output signal of a CCD image sensor is sampled twice during one pixel period: once at the reference interval
and again at the data interval. Subtracting these two samples extracts the video information of the pixel as well
as removes any noise which is common (or correlated) to both intervals. CDS is critical to reduce the reset noise
and the low-frequency noise that is present on the CCD output signal. Figure 5 shows the block diagram of the
CDS.
Figure 5. Block Diagram of CDS and Input Clamp
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