Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 12 Bit VQFN 36

VSP2582

Not Recommended for New Designs

VSP2582

www.ti.com

SBES002B –JUNE 2008–REVISED JUNE 2011

CCD ANALOG FRONT-END FOR DIGITAL CAMERAS

Check for Samples: VSP2582

FEATURES

DESCRIPTION

The VSP2582 is a complete mixed-signal processing

• CCD Signal Processing:

IC for digital cameras that provides correlated double

– 36-MHz Correlated Double Sampling (CDS)

sampling (CDS) and analog-to-digital conversion

• 12-Bit Analog-to-Digital Conversion:

(ADC) for the output of charge-coupled device (CCD)

array. The CDS extracts video information of the

– 36-MHz Conversion Rate

pixels from the CCD signal, and the ADC converts it

– No Missing Codes Ensured

to a digital signal. For varying illumination conditions,

• 78-dB Input-referred SNR (at CDS Gain 0 dB)

–9 dB to +35 dB very stable gain control is provided.

This gain control is linear in dB. Input signal clamping

• Programmable Black Level Clamping

and offset correction of the input CDS are also

• Programmable Gain Amp (PGA):

provided.

–9 dB to +35 dB, –3 dB to +9 dB

Offset correction is performed by an Optical Black

by Analog Front Gain (CDS)

(OB) level calibration loop, and held at a calibrated

–6 dB to +26 dB by Digital Gain

black level clamping for an accurate black level

• Portable Operation:

reference. Additionally, the black level is quickly

– Low Voltage: 2.7 V to 3.6 V

recovered after a gain change.

– Low Power: 85 mW at 3.0 V and 36 MHz,

The VSP2582 is available in a QFN-36 package, and

1 mW in Standby Mode

operates from a single +3 V supply. The RHH

• QFN-36 Package

package features an exposed thermal pad, resulting

in substantially improved thermal performance.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
Not Recommended for New Designs VS P2 VSP2582 582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 CCD ANALOG FRONT-END FOR DIGITAL CAMERAS Check for Samples: VSP2582 FEATURES DESCRIPTION • The VSP2582 is a complete mixed-signal processing IC for digital cameras that provides correlated double sampling (CDS) and analog-to-digital conversion (ADC) for the output of charge-coupled device (CCD) array.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 ELECTRICAL CHARACTERISTICS Over operating free-air temperature range (unless otherwise noted). VSP2582RHN PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 36 MHz 12 Conversion rate Bits ANALOG INPUT (CCDIN) Input signal level for full-scale out CDS gain = 0 dB, DPGA gain = 0 dB 1000 mV Maximum input range CDS gain = –3 dB, DPGA gain = 0 dB 1300 mV Input capacitance 15 Input limit –0.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over operating free-air temperature range (unless otherwise noted). VSP2582RHN PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS Logic family CMOS Input voltage Input current VT+ LOW to HIGH threshold voltage 1.7 VT– HIGH to LOW threshold voltage 1.0 V V IIH Logic HIGH, VIN = +3 V ±20 μA IIL Logic LOW, VIN = 0 V ±20 μA VCC + 0.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 PIN CONFIGURATION COB BYPP BYP CCDIN AGND AGND VCC VCC AGND RHH AND RHN PACKAGES QFN-36 (TOP VIEW) 27 26 25 24 23 22 21 20 19 VCC 30 16 CLPOB AGND 31 15 CLPDM SLOAD 32 14 VCC SDATA 33 13 ADCCK SCLK 34 12 DGND B0 (LSB) 35 11 VDD B1 36 10 B11 (MSB) 2 3 4 5 6 7 8 9 B10 1 B9 SHP B8 17 B7 29 B6 REFP B5 SHD B4 18 B3 28 B2 REFN Table 1.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. TYPE (1) AGND 22 P Analog ground AGND 23 P Analog ground CCDIN 24 AI CCD signal input DESCRIPTION BYP 25 AO Internal reference bypass to ground by 0.1 μF BYPP 26 AO Internal reference bypass to ground by 1000 pF COB 27 AO OB loop feed back capacitor REFN 28 AO Internal reference bypass to ground by 0.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 TIMING SPECIFICATIONS CCD N N+1 N+2 N+3 tWP SHP tPD tWD tS tWD SHD tINHIBIT2 tS tCKP tADC tADC tINHIBIT1 ADCCK tOD B0-B9 N-6 N-5 N-4 N-3 Figure 1. TG High-Speed Pulse Specifications TIMING CHARACTERISTICS (36-MHz Operation) SYMBOL PARAMETER MIN tCKP Clock period 27.7 TYP MAX tADC ADCCK high or low level 6.5 13.8 21.2 UNIT ns ns tWP SHP pulse width 5.9 6.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com tINHIBIT1 27.77ns SHP ADCCK (rise) tINHIBIT1 tINHIBIT1 tINHIBIT1 tINHIBIT1 9ns ADCCK 13ns Note that in condition of OD (Output delay) = 00 tINHIBIT2 27.77ns SHP ADCCK (rise) tINHIBIT2 tINHIBIT2 tINHIBIT2 tINHIBIT2 8ns ADCCK 0ns Figure 2.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 SLOAD tXH tXS tCKL tCKP tCKHX tCKH SCLK tDH tDS SDATA LSB A0 A1 A2 MSB D5 D4 2 Bytes Figure 3.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com APPLICATION INFORMATION Overview The VSP2582 is a complete mixed-signal IC that contains all of the key features associated with processing the CCD imager output signal in a video camera, digital still camera, security camera, or similar application. A simplified block diagram is shown in Figure 4.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 Input Clamp The buffered CCD output is capacitively coupled to the VSP2582. The purpose of the input clamp is to restore the dc component of the input signal that was lost with ac coupling and establish the desired dc bias point for the CDS. Figure 5 also shows the block diagram of the input clamp. The input level is clamped to the internal reference voltage REFP (1.5 V) during the dummy pixel interval.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com At the CDS circuit, the CCD offset is compensated as a difference between the reference level and the data level of the OB pixel. The compensated signal levels are recognized as actual OB levels, and outputs are clamped to OB levels set by the serial interface. These OB levels are the base of black for the effective pixel period thereafter.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 Programmable Gain The VSP2582 has a wide programmable gain range of –9 dB to 35 dB. The desired gain is set as a combination of the CDS gain and Digital Programmable Gain Amplifier (DPGA). The CDS gain can be programmed over the range of –3 dB to 9 dB in 3-dB steps. Digital gain can be programmed from –6 dB to 26 dB by a 0.03125 dB step. Both gain settings are controlled through the serial interface.
PAGE 14
Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com The CCD has several dummy and Optical Black pixels per line. The placement of these pixels depends on the CCD manufacturer, but are usually at the beginning and end of the line with the imaging pixels in between. During the time the dummy pixels are being read from the CCD, it is recommended to activate CLPDM. During the time the Optical Black pixels are being read, it is recommended to activate CLPOB.
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Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 SERIAL INTERFACE All functions and settings of the VSP2582 are controlled through the serial interface. The VSP2582 serial interface is composed of three signals: SDATA, SCLK, and SLOAD. SDATA data are sequentially stored to shift into the register at a rising edge or SCLK, and shift register data are stored in a parallel latch at an SLOAD rising edge.
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Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com Clk-Pol-ctrl Register (Address: h000) Clk-Pol-ctrl selects the active polarity of CLPDM, CLPOB, and SHP/SHD.
PAGE 17
Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 D-PGA Register (Address: h006 and h007) D-PGA_U D-PGA_L D[3:0] ANALOG GAIN DEFAULT Digital PGA gain is givens following equation. Gain (dB) = (D-PGA • 0.03125 ) – 6 Where: D-PGA is decimal value of 10-bit data which is combined D-PGA_U and D-PGA_L. DPGA_U is MSB side of D-PGA.
PAGE 18
Not Recommended for New Designs VSP2582 SBES002B – JUNE 2008 – REVISED JUNE 2011 www.ti.com Because of the high operating speed, the converter also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This interference requires the supply and reference pins to be sufficiently bypassed. In most cases, a 0.1-μF ceramic-chip capacitor is adequate to decouple the reference pins.
PAGE 19
Not Recommended for New Designs VSP2582 www.ti.com SBES002B – JUNE 2008 – REVISED JUNE 2011 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2008) to Revision B Page • Added last sentence to Description section ..........................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant VSP2582RHHR VQFN RHH 36 2500 330.0 13.4 6.6 6.6 1.15 8.0 12.0 Q1 VSP2582RHNR VQFN RHN 36 2000 330.0 13.4 6.6 6.6 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VSP2582RHHR VQFN RHH 36 2500 367.0 367.0 45.0 VSP2582RHNR VQFN RHN 36 2000 367.0 367.0 35.
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