Datasheet

PRODUCTPREVIEW
t
CKH
t
CKL
t
DS
t
DH
t
XH
LSB
A0
SDATA
MSB
D5
SCLK
S
LOAD
t
CKHX
R
LOAD
t
RL
t
WR
t
XS
t
CKP
TwoBytes
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
SBES008 –AUGUST 2008 www.ti.com
SERIAL INTERFACE TIMING
Figure 2. Serial Interface Timing
Table 3. TIMING CHARACTERISTICS FOR
Figure 2
PARAMETER
(1) (2)
MIN TYP MAX UNIT
t
CKP
Clock period 50 ns
t
CKH
Clock high pulse width 25 ns
t
CKL
Clock low pulse width 25 ns
t
DS
Data setup time 15 ns
t
DH
Data hold time 15 ns
t
XS
S
LOAD
to SCLK setup time 20 ns
t
XH
SCLK to S
LOAD
hold time 20 ns
t
CKHX
SCLK hold time of final SCLK 0 ns
t
RL
SCLK to R
LOAD
setup time 20 ns
t
WR
R
LOAD
pulse width 20 ns
(1) t
PD
+ t
WD
should be nearly equal to t
DP
+ t
WP
.
(2) The t
WP
and t
WD
specifications assume a driving impedance of less than 30 Ω at CCDIN.
The data shift operation should decode at the rising edges of SCLK while S
LOAD
is low. Furthermore, the input
address and data of the serial data stream are loaded to the parallel latch in the VSP2560/62/66 at the rising
edge of S
LOAD
.
8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Links: VSP2560 VSP2562 VSP2566