Datasheet

PRODUCTPREVIEW
N N+1 N+2 N+3
t
WP
t
WD
t
S
t
S
t
OD
N 6- N 5-
N 4-
N 3-
CCD
SHP
SHD
ADCCK
B0 B9-
t
PD
t
DP
t
CKP
t
ADC
t
ADC
t
INHIBIT
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
www.ti.com SBES008 –AUGUST 2008
TIMING CHARACTERISTICS
TG HIGH-SPEED PULSE
Figure 1. TG High-Speed Pulse Timing
Table 2. TIMING CHARACTERISTICS FOR Figure 1
PARAMETER
(1) (2)
MIN TYP MAX UNIT
t
CKP
Clock period 27.7 ns
t
ADC
ADCCK high or low level 13.8 ns
t
WP
SHP pulse width 6.9 ns
t
WD
SHD pulse width 6.9 ns
t
PD
SHP trailing edge to SHD leading edge 6.9 ns
t
DP
SHD trailing edge to SHP leading edge 6.9 ns
t
S
Sampling delay 3 ns
Inhibited clock period (from rising edge of SHP to
t
INHIBIT
–3 10 ns
rising edge of ADCCK)
t
OD
Output delay
(3)
0 5 ns
DL Data latency 6 Clocks
(1) t
PD
+ t
WD
should be nearly equal to t
DP
+ t
WP
.
(2) The t
WP
and t
WD
specifications assume a driving impedance of less than 30 Ω at CCDIN.
(3) Data output delay by AFE-ctrl(2) register is 0 ns.
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