Datasheet

PRODUCTPREVIEW

Not Recommended for New Designs

VSP2560

VSP2562

VSP2566

SBES008 –AUGUST 2008

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POWER SUPPLY, GROUNDING, AND DEVICE COUPLING RECOMMENDATIONS

The VSP2560/62/66 incorporate a high-precision, high-speed ADC and analog circuitry that are vulnerable to any

extraneous noise from the rails or elsewhere. For this reason, the VSP2560/62/66 should be treated as an

analog component. Furthermore, though these devices have several supply pins, all supply pins except for VDD

should be powered by only the analog supply of the system. This design ensures the most consistent results

because digital power lines often carry high levels of wideband noise that would otherwise be coupled into the

device and degrade the achievable performance.

Proper grounding, short lead length, and the use of ground planes are also very important for high-frequency

designs. Multilayer printed circuit boards (PCBs) are recommended to deliver the best performance because they

offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers,

etc. It is highly recommended that the analog and digital ground pins of the VSP2560/62/66 be joined together at

the IC and be connected only to the analog ground of the system. The driver stage of the digital outputs (B15,

B11, and B[9:0]) is supplied through a dedicated supply pin (VDD) and should be separated from the other

supply pins completely, or at least with a ferrite bead. It is also recommended to keep the capacitive loading on

the output data lines as low as possible (typically less than 15 pF). Larger capacitive loads demand higher

charging current as a result of surges that can feed back into the analog portion of the VSP2560/62/66 and affect

performance.

If possible, external buffers or latches should be used. This configuration provides the added benefit of isolating

the VSP2560/62/66 from any digital noise activities on the data lines. In addition, resistors in series with each

data line may help in minimizing the surge current.

Because of the high operation speed, the converter also generates high-frequency current transients and noises

that are fed back into the supply and reference lines. This condition requires the supply and reference pins to be

sufficiently bypassed. In most cases, a 0.1-μF ceramic-chip capacitor is adequate to decouple the reference pins.

Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1 μF to 22 μF) and

ceramic (0.1 μF) capacitors. The effectiveness of the decoupling largely depends on the proximity to the

individual pin. VDD should be decoupled to the proximity of DGND. Special attention must be paid to the

bypassing of COB and BYPP because these capacitor values determine important analog performance of the

device. Although the recommended value for COB is 0.1 μF and BYPP is 1000 pF, it is better to adjust the

capacitor for BYPP in the case.

Product Folder Links: VSP2560 VSP2562 VSP2566