Datasheet

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VSP2560
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www.ti.com SBES008 –AUGUST 2008
A-PGA Register Description (Address = 008h)
The A-PGA register describes the CDS gain control, as shown in Table 13.
Table 13. CDS Gain Control
D2 D1 D0 ANALOG GAIN (dB)
0 0 0 0 (default)
0 0 1 6
0 1 0 12
0 1 1 18
1 1 1 –3
Power Register Description (Address = 009h)
The power register describes the power control settings, as shown in Table 14.
Table 14. Power Controls
DATA BIT NAME DESCRIPTION DEFAULT
00 = x1, 01 = x2, 10 = x4, 11 = x8
D[1:0] OB loop IDAC output current 00
DAC power control for OB loop time constant
0 = Normal CDS power 1 = Reduce CDS power
D2 CDS power trim 0
CDS power control for settling time
0 = Normal ADC power 1 = Reduce ADC power
D3 ADC power trim 0
ADC power control
0 = Normal Ref power 1 = Reduce Ref power
D4 Ref power trim 0
REF bias power control
0 = Normal GBA power 1 = Reduce GBA power
D5 GBA power trim 0
CDS gain power control
DAC A Register Description (Address = 00Ah and 00Bh)
The DAC B register describes the codes for DAC1, as shown in Table 15.
Table 15. DAC1
DAC1_U DAC1_L ANALOG GAIN DEFAULT
General-purpose, 8-bit DAC1 input code.
D[1:0] D[5:0] 00 000000
DAC1_U is the MSB side code.
DAC B Register Description (Address = 00Ch and 00Dh)
The DAC B register describes the codes for DAC2, as shown in Table 16.
Table 16. DAC2
DAC2_U DAC2_L ANALOG GAIN DEFAULT
General-purpose, 8-bit DAC2 input code.
D[1:0] D[5:0] 00 000000
DAC1_U is MSB side code.
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