Datasheet

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VSP2560
VSP2562
VSP2566
SBES008 –AUGUST 2008 www.ti.com
Clamp Register Description (Address = 004h)
The clamp levels for the VSP2560/62/66 are shown in Table 10.
Table 10. Clamp Levels
CLAMP LEVEL CLAMP LEVEL CLAMP LEVEL
D4 D3 D2 D1 D0 (VSP2560) (VSP2562) (VSP2566)
0 0 0 0 0 16 (LSB) 64 (LSB) 1024 (LSB)
0 0 0 0 1 18 (LSB) 72 (LSB) 1152 (LSB)
— — — —
0 0 1 1 1 30 (LSB) 120 (LSB) 1920 (LSB)
0 1 0 0 0 32 (LSB) (default) 128 (LSB) (default) 2048 (LSB) (default)
0 1 0 0 1 34 (LSB) 136 (LSB) 2176 (LSB)
— — — —
1 1 1 1 0 76 (LSB) 304 (LSB) 4864 (LSB)
1 1 1 1 1 78 (LSB) 312 (LSB) 4992 (LSB)
Hot-Pixel Register Description (Address = 005h)
The hot-pixel register defines the threshold level for input signals from the saturated pixel (as shown in Table 11),
which is mainly caused by a defective pixel during the OB term.
Table 11. Saturated Pixel Threshold Level
DATA BIT NAME DESCRIPTION DEFAULT
The hot pixel rejection level is given as:
For the VSP2560 (10-bit), R
L
(LSB) = 16 × (d[4:0] + 1)
D[4:0] Hot pixel rejection level For the VSP2562 (12-bit), R
L
(LSB) = 64 × (d[4:0] + 1) 11111
For the VSP2566 (16-bit), R
L
(LSB) = 1024 × (d[4:0] + 1)
Where R
L
is the difference in level from the OB level.
D5 Hot pixel rejection disable 0 = Disabled 1 = Enabled 1
D-PGA Register Description (Address = 006h and 007h)
The D-PGA register defines the digital PGA gain, as shown in Table 12.
Table 12. DPGA Gain
D-PGA_U D-PGA_L ANALOG GAIN DEFAULT
Digital PGA gain is given as:
Gain (dB) = (D-PGA × 0.03125) – 6
Where D-PGA is the decimal value of 10-bit data that are combined
D[3:0] D[5:0] D-PGA = 00 1100 0000b = 0 dB
D-PGA = 0 (decimal) = –6 dB
D-PGA = 192 (decimal) = 0 (default)
D-PGA = 1023 (decimal) = 26 dB
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