Datasheet

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VSP2560
VSP2562
VSP2566
www.ti.com SBES008 –AUGUST 2008
Clk-Pol-Ctrl Register Description (Address = 000h)
The Clk-Pol-Ctrl register selects the active polarity of CLPDM, CLPOB, and SHP/SHD, as shown in Table 6.
Table 6. Active Polarity Selection
DATA BIT NAME DESCRIPTION DEFAULT
D1 Register update control 0 = Real-time update 1 = Update by R
LOAD
0
0 = Update at rising edge of 1 = Update at falling edge of
D2 R
LOAD
polarity 0
R
LOAD
R
LOAD
(1)
D3 CLPDM polarity 0 = Active low 1 = Active high 0
D4 CLPOB polarity 0 = Active low 1 = Active high 0
D5 SHP/SHD polarity 0 = Active low 1 = Active high 0
(1) When data bit D2 is set as '1', the register update timing is controlled by R
LOAD
regardless if D1 is set as '0' or '1'.
AFE-Ctrl(1) Register Description (Address = 001h)
The AFE-Ctrl(1) register controls the standby settings, as shown in Table 7.
Table 7. Standby Setting
DATA BIT NAME DESCRIPTION DEFAULT
D0 Standby 0 = Normal operation 1 = Standby 0
D1 DAC1 standby 0 = Operating 1 = Standby 1
D2 DAC2 standby 0 = Operating 1 = Standby 1
D3 Test enable 0 = Disabled 1 = Enabled 0
AFE-Ctrl(2) Register Description (Address = 002h)
The AFE-Ctrl(2) register controls the data output setting, as shown in Table 8.
Table 8. Data Output Setting
DATA BIT NAME DESCRIPTION DEFAULT
00 = 0 ns
01= 2 ns
D[1:0] Data output delay 00
10 = 4 ns
11 = 6 ns
D4 Output enabled 0 = Enabled 1 = Hi-Z 0
S-Delay Register Description (Address = 003h)
The S-delay register controls the SHD sampling start time from the rising edge of SHP. SHD sampling is shown
in Table 9.
Table 9. SHD Sampling
DATA BIT NAME DESCRIPTION DEFAULT
00 = 0 ns
01= 2 ns
D[1:0] Sampling delay for SHD 00
10 = Do not use
11 = Do not use
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