Datasheet

PRODUCTPREVIEW
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
www.ti.com SBES008 –AUGUST 2008
VOLTAGE REFERENCE
All reference voltages and bias currents used in these devices are created from internal bandgap circuitry. The
VSP2560/62/66 have symmetrical, independent voltage references for each channel.
Both channels of the CDS and the ADC use three primary reference voltages: REFP (1.5 V), REFN (1.0 V), and
CM (1.25 V) of an individual reference. REFP and REFN are buffered on-chip. CM is derived as the mid-voltage
of the resistor chain internally connecting REFP and REFN. The ADC full-scale range is determined by twice the
difference voltage between REFP and REFN. REFP, REFN, and CM should be heavily decoupled with
appropriate capacitors.
HOT PIXEL REJECTION
Sometimes the OB pixel output signal from the CCD includes an unusual level signal that is caused by pixel
defection. If this level reaches a full-scale level, it may affect OB level stability. The VSP2560/62/66 has a
function that rejects any unusually large pixel level (hot pixels) in the OB pixel. This function may contribute to
CCD yield improvement, caused by OB pixel failure.
Rejection levels for hot pixels are programmed through the serial interface. When a hot pixel comes from the
CCD, the VSP2560/62/66 omit it and replaces the previous pixel level for OB level calculation.
GENERAL-PURPOSE, 8-BIT DAC (DAC1, DAC2)
The VSP2560/62/66 incorporate two identical 8-bit DACs. These DACs are for user-definable options such as iris
control and sub-bias voltage control of the CCD imager. The input data for these DACs are set by the written
data through the serial interface (refer to the Serial Interface section for more detail). DAC input data that are all
'0's correspond to a minimum output voltage of 0.1 V. In a similar manner, all '1's correspond to a maximum
output voltage of 2.9 V. For minimizing power consumption, DAC standby is recommend when the application
does not use a DAC.
SERIAL INTERFACE
All functionality and parameters of the VSP2560/62/66 are controlled through the serial interface. The serial
interface of the VSP2560/62/66 is composed of three signals: SDATA, SCLK, and S
LOAD
. SDATA data are
sequentially stored in the shift register at the rising edge of SCLK, and shift register data are stored in the parallel
latch of the rising edge of S
LOAD
. Before a writing operation, S
LOAD
must go low, and remain low during writing
(refer to the Serial Interface Timing description of the Timing Characteristics).
The serial interface command is composed of a 10-bit address and 6-bit data. Fundamentally, the writing
operation is a two-byte write mode. In this mode, one serial interface command is sent by a combination of
address and data. The 10-bits address should be sent primarily as LSB first, and followed 6-bit data also sent as
LSB first. The 6-bits command data is stored to respective register by 10-bits of address when rising edge of
S
LOAD
. The stored serial command data immediately affects the rising edge of S
LOAD
.
The VSP2560/62/66 are also supported by a continuous writing mode. When the input serial data are longer than
two bytes (16-bits), the following data stream is automatically recognized as the data of the next address. In this
mode, 6-bit serial command data are stored in the respective register immediately when the data are fetched.
Address and data should be sent as LSB-first as well as in a two-byte writing mode. If the data bits do not fill up
six bits at the end of the data stream, any blank data bits are ignored.
Register updates can be controlled by R
LOAD
. When D1 of the Clk-Pol-Ctrl register is set to '1', the register data
update timing synchronizes the rising edge of R
LOAD
. In this operation, serial interface data are stored in the
buffer register until the next rising edge of R
LOAD
, and are updated simultaneously by that rising edge. If the rising
edge of R
LOAD
occurs during continuous writing, any updated data are completed during the data streams before
the rising edge of R
LOAD
. The setting for the serial interface registers is described in the Serial Interface Register
Description section.
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