Datasheet

PRODUCTPREVIEW
CCD
Output
OB
ImagePixel ImagePixel
OBPixel
DM
Pixel
CLPOB
CLPDM
1H
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
SBES008 –AUGUST 2008 www.ti.com
STANDBY MODE AND POWER TRIM FUNCTION
For the purpose of saving power, the VSP2560/62/66 devices can be put into a standby mode through the serial
interface control when the device is not in use. In this mode, all the functional blocks are disabled and the digital
outputs are set to '0'. The consumption current drops to approximately 2 mA. Only 10 ms is required to restore
the device from standby mode. A general-purpose DAC also enables standby mode independently, which allows
the device to enter standby mode and resume normal operation through the serial interface.
The VSP2560/62/66 provide a power trim function. This function trims the power of the CDS, ADC, reference
source, and gain boost amplifier of the ADC (GBA). Power consumption can be reduced through this trim
function, though it is not recommended at 36-MHz operation because accuracy may degrade. This function is
useful for low sampling rate operation.
TIMINGS
The CDS and ADC are operated by SHP and SHD, and the derivative timing clocks are generated by the on-chip
timing generator. The output register and decoder are operated by ADCCK. The digital output data are
synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and the output
data is described in the Timing Characteristics section. CLPOB is used to activate the black level clamp loop
during the OB pixel interval and CLPDM is used to activate the input clamping during the dummy pixel interval. In
standby mode ADCCK, SHP, SHD, CLPOB, and CLPDM are internally masked and pulled high.
The data output timing can be delayed by the AFE-Ctrl(2) register. Fundamentally, the data output timing should
be adjusted through ADCCK timing, although that is effective when exceeding adjust range is needed.
As explained in the Input Clamp and Optical Black Level (OB) Loop and OB Clamp Level sections, CLPOB is
used for controlling the OB loop that compensates CCD offset automatically, and CLPDM is used for charging
the input clamp voltage to the capacitor C
IN
that is connected to CCDIN. To obtain proper operation, both CLPOB
and CLPDM should be active immediately before the timing begins, as described in the following paragraphs.
The CCD has several dummy and OB pixels. Typically, the dummy pixel is placed at the start of the line and the
OB pixel is placed after the effective pixel. The timing recommendation is for CLPDM to activate during the
dummy pixel period, and for CLPOB to activate during the OB pixel period. Any active period should include the
dummy and OB pixels in the same period.
In some cases, the dummy pixel is defined as only '2' or some other small value. The VSP2560/62/66 may
operate with a small defined dummy pixel value, but '2' is too small. For instance, if the discharge of the input
clamp from C
IN
is large, the VSP2560/62/66 could not recover from it. In this case, CLPDM can share the OB
pixel with CLPOB. Although a longer CLPOB period is preferred, approximately 20 pixels are theoretically
enough to return stable operation to normal conditions, depending on the situation (such as the noise of OB
pixels). CLPDM also requires 10 to 20 pixels. In the event the OB pixel is only approximately 30 pixels, it should
be shared as 20 pixels for CLPOB and 10 pixels for CLPDM. In order to get stable OB levels, CLPOB and
CLPDM need to be active during different parts of the CCD pixels.
Figure 7 shows a timing diagram for CLPOB and CLPDM. The functionality of SHP, SHD, CLPOB, CLPDM, and
R
LOAD
is active at low periods or at the rising edge of the default setting of the serial interface; each active
polarity can be selected by register settings.
Figure 7. CLPOB and CLPDM Timing Diagram
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Product Folder Links: VSP2560 VSP2562 VSP2566