Datasheet

PRODUCTPREVIEW
128 256
10240
InputCodeforGainControl(0to1023)
30
25
20
15
10
5
0
-5
-10
Gain(dB)
384 512 640 768 896
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
www.ti.com SBES008 –AUGUST 2008
The OB clamp level (digital output value) can be externally set through the serial interface by inputting the digital
code to the OB clamp level register. The digital codes to be input and the corresponding OB clamp levels are
shown in Table 4.
Table 4. Input Codes and OB Clamp Levels to be Set
CLAMP LEVEL
CODE VSP2560 (10-Bit) VSP2562 (12-Bit) VSP2566 (16-Bit)
00000b 16 LSB 64 LSB 1024 LSB
00001b 18 LSB 72 LSB 1152 LSB
— — — —
00110b 28 LSB 112 LSB 1792 LSB
00111b 30 LSB 120 LSB 1920 LSB
01000b (default) 32 LSB 128 LSB 2048 LSB
01001b 34 LSB 136 LSB 2176 LSB
— — — —
11110b 76 LSB 304 LSB 4864 LSB
11111b 78 LSB 312 LSB 4992 LSB
PROGRAMMABLE GAIN
The VSP2560/62/66 have gains that range from –9 dB to 44 dB. The desired gain is set as a combination of
CDS gain and the digital programmable gain amplifier (DPGA). The CDS gain can be programmed from 0 dB to
18 dB in 6-dB steps, and has a –3-dB gain for the large input signal (such as over 1 V). Digital gain can be
programmed from –6 dB to 26 dB in 0.032-dB steps. Both gain controls are managed through the serial
interface. The digital gain changes linearly in proportion to the settling code. Figure 6 shows the relationship of
input code to digital gain.
Figure 6. Settling Code versus Digital Gain
The recommended usage of the combination of CDS and digital gain is to adjust the CDS gain first, primarily as
an image signal amplification; afterwards, use the digital gain as an adaptive gain control. The wide range of
digital gain covers the necessary gain range on most typical applications. If the CDS gain must be changed,
however, it is recommended to change it during a period that does not affect picture quality (such as a blanking
period).
PRE-BLANKING AND DATA LATENCY
The VSP2560/62/66 have a pre-blanking function. When PBLK is low, the digital outputs all become '0' at the
eighth rising edge of ADCCK after PBLK goes low, to accommodate the clock latency of the VSP2560/62/66.
The data latency of this family of devices is six clock cycles. The digital output data are transmitted at the rising
edge of ADCCK with a delay of six clock cycles.
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