Datasheet

PRODUCTPREVIEW

INP

REFP

CCDIN

SHP/SHD

SHD

SHP

CCD

Input

SHP

CLPDM

Not Recommended for New Designs

VSP2560

VSP2562

VSP2566

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SBES008 –AUGUST 2008

CORRELATED DOUBLE SAMPLER (CDS)

The output signal of a CCD image sensor is sampled twice during one pixel period: once at the reference

interval, and again at the data interval. Subtracting these two samples extracts the pixel video information and

removes any noise that is common (or correlated) to both intervals. Thus, it is very important to reduce the reset

noise and low-frequency noises that are present on the CCD output signal through the CDS. Figure 4 shows a

block diagram of the CDS.

Figure 4. CDS and Input Clamp Block Diagram

INPUT CLAMP

The buffered CCD output is capacitively coupled to the VSP2560/62/66. The purpose of the input clamp is to

restore the dc component of the input signal that was lost with the ac coupling, and establish the desired dc bias

point for the CDS. The block diagram of Figure 4 also shows the input clamp. The input level is clamped to the

internal reference voltage, REFP (1.5 V), during the dummy pixel interval. More specifically, the clamping

function becomes active when both CLPDM and SHP are active.

Immediately after device power-on, the input capacitor clamp voltage is not charged. For fast charge-up of the

clamp voltage, the VSP2560/62/66 provide a boost-up circuit.

16-BIT ADC

The VSP2560/62/66 include a high-speed, 16-bit ADC. This ADC uses a fully-differential pipelined architecture

with correction. This architecture, incorporating ADC correction, is very advantageous for realizing better linearity

for a smaller signal level as a result of the large linearity errors that tend to occur at specific points in the full-

scale range; linearity also improves for a signal level below that specific point. The ADC ensures 16-bit resolution

across the entire full-scale range.

Product Folder Links: VSP2560 VSP2562 VSP2566