Datasheet

PRODUCTPREVIEW
Decoder
DPGA
Clamp
Current DAC
Buffer
Digital
Output
10/12/16-Bit
GainControl
FromSerialInterface
FromInternal
TimingCircuit
InternalClocks(SHP/SHD, ADCCK,CLPOB,CLPDM)
16-Bit ADC
CCDIN
CCDOut
Signal
CDS
BYPP COB
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
SBES008 –AUGUST 2008 www.ti.com
SYSTEM DESCRIPTION
OVERVIEW
The VSP2560/62/66 are a family of complete mixed-signal ICs that contain all of the key features associated with
the processing of the charge-coupled device (CCD) imager output signal in a video camera, digital still camera,
security camera, or other similar applications. Figure 3 shows a simplified block diagram of the VSP2560/62/66.
The VSP2560/62/66 include a correlated double sampler (CDS), a programmable gain amplifier (PGA), an
analog-to-digital converter (ADC), an input clamp, an optical black (OB) level clamp loop, a serial interface,
timing control, and a reference voltage generator. It is recommend that an off-chip emitter follower be placed
between the CCD output and the VSP2560/62/66 CCDIN input. All of the functions and parameters (such as
PGA gain control, operation mode, and other settings) can be changed through the serial interface. All
parameters are reset to the default value when the RESET pin goes to low asynchronously from the clocks.
The VSP2560/62/66 also provide a two-channel, general-purpose, 8-bit digital-to-analog converter (DAC). This
DAC can be applied to various applications, such as CCD bias control, iris control, and so forth.
Figure 3. Simplified Block Diagram
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Product Folder Links: VSP2560 VSP2562 VSP2566