Datasheet
PRODUCTPREVIEW
Decoder
DPGA andOutputRegister
Clamp
CurrentDAC
Buffer
16-Bit ADCCDS
8-BitDAC1
InternalReference
Digital
Output
SHP/SHD
ADCCK
CLPDM
GainSetting
Internal TimingCircuit
SerialInterfaceandRegister
RESET
PBLK
CLPOB
CLPDM
SHD
SHP
ADCCK
R
LOAD
S
LOAD
SCLK
SDATA
DACOUTPUT 1
CCDIN
CCDOut
Signal
8-BitDAC2
DACOUTPUT 2
BYPP COB BYP REFP CM REFN
Not Recommended for New Designs
VSP2560
VSP2562
VSP2566
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SBES008 –AUGUST 2008
FUNCTIONAL BLOCK DIAGRAM
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