Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 12 Bit LQFP 48

PRODUCTPREVIEW

Not Recommended for New Designs

VSP2560

VSP2562

VSP2566

www.ti.com

SBES008 –AUGUST 2008

CCD ANALOG FRONT-END FOR DIGITAL CAMERAS

Check for Samples: VSP2560, VSP2562, VSP2566

FEATURES

• Two-Channel, General-Purpose, 8-Bit DAC

• QFP-48 Package

• CCD Signal Processing:

DESCRIPTION

– 36-MHz Correlated Double Sampling (CDS)

The VSP2560/62/66 are a family of complete mixed-

• Output Resolution:

signal processing ICs for digital cameras that provide

– VSP2560 (10-Bit)

correlated double sampling (CDS) and analog-to-

digital conversion for the output of CCD arrays. The

– VSP2562 (12-Bit)

CDS extracts the pixel video information from the

– VSP2566 (16-Bit)

CCD signal, and the analog-to-digital converter (ADC)

• 16-Bit Analog-to-Digital Conversion:

converts the digital signal. For varying illumination

conditions, a very stable gain control of –9 dB to 44

– 36-MHz Conversion Rate

dB is provided. The gain control is linear in dB. Input

– No Missing Codes Ensured

signal clamping and offset correction of the input

• 80-dB Input-Referred SNR (at Gain = 12 dB)

CDS are also provided.

• Programmable Black Level Clamping

Offset correction is performed by the optical black

• Programmable Gain Amp (PGA):

(OB) level calibration loop, and is held in calibrated

black level clamping for an accurate black level

– –9 dB to +44 dB

reference. Additionally, the black level is quickly

– –3 dB to +18 dB (Analog Front Gain)

recovered after gain changes. The VSP2560/62/66

– –6 dB to +26 dB (Digital Gain)

are available in LQFP-48 packages and operate from

• Portable Operation:

single +3 V supplies.

– Low Voltage: 2.7 V to 3.6 V

– Low Power: 86 mW at 3.0 V, 36 MHz

– Low Power: 6 mW (Standby Mode)

Table 1. FEATURE COMPARISON BY DEVICE

TRANSFER CHARACTERISTICS

(LSB) OB CLAMP LOOP (LSB)

RESOLUTION PROGRAMMABLE OBCLP

DEVICE (Bits) DNL INL RANGE LEVEL OB LEVEL

VSP2560 10 ±0.5 ±1 16 to 78 32 2

VSP2562 12 ±0.5 ±2 64 to 312 128 8

VSP2566 16 ±2 ±32 1024 to 4992 2048 128

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

Summary of content (32 pages)

PAGE 1
Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.
PAGE 2
Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 ELECTRICAL CHARACTERISTICS: VSP2560 All specifications at TA = +25°C, all power-supply voltages = +3.0 V, and conversion rate = 36 MHz, no load, unless otherwise noted.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com ELECTRICAL CHARACTERISTICS: VSP2562 All specifications at TA = +25°C, all power-supply voltages = +3.0 V, and conversion rate = 36 MHz, no load, unless otherwise noted.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 ELECTRICAL CHARACTERISTICS: VSP2566 All specifications at TA = +25°C, all power-supply voltages = +3.0 V, and conversion rate = 36 MHz, no load, unless otherwise noted.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, no load, unless otherwise noted. VSP2560PT, VSP2562PT, VSP2566PT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GENERAL-PURPOSE, 8-BIT DAC (CHANNELS A, B) Minimum output voltage Input code = 0000 0000 0.1 V Maximum output voltage Input code = 1111 1111 2.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 TIMING CHARACTERISTICS TG HIGH-SPEED PULSE N CCD N+1 N+2 N+3 tWP tS SHP tPD tDP tWD tS SHD tCKP tADC tADC tINHIBIT ADCCK B0-B9 N-6 N-5 PRODUCT PREVIEW tOD N-3 N-4 Figure 1. TG High-Speed Pulse Timing Table 2. TIMING CHARACTERISTICS FOR Figure 1 PARAMETER (1) (1) (2) (3) (2) MIN tCKP Clock period 27.7 tADC ADCCK high or low level 13.8 ns tWP SHP pulse width 6.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com SERIAL INTERFACE TIMING RLOAD tWR tRL SLOAD tXS tXH tCKH tCKL tCKHX tCKP SCLK tDH tDS SDATA LSB A0 MSB D5 Two Bytes PRODUCT PREVIEW Figure 2. Serial Interface Timing Table 3.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com SYSTEM DESCRIPTION OVERVIEW The VSP2560/62/66 are a family of complete mixed-signal ICs that contain all of the key features associated with the processing of the charge-coupled device (CCD) imager output signal in a video camera, digital still camera, security camera, or other similar applications. Figure 3 shows a simplified block diagram of the VSP2560/62/66.
PAGE 17
Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 CORRELATED DOUBLE SAMPLER (CDS) The output signal of a CCD image sensor is sampled twice during one pixel period: once at the reference interval, and again at the data interval. Subtracting these two samples extracts the pixel video information and removes any noise that is common (or correlated) to both intervals.
PAGE 18
Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com OPTICAL BLACK LEVEL (OB) LOOP AND OB CLAMP LEVEL The VSP2560/62/66 have a built-in optical black (OB) offset self-calibration circuit (OB loop) that compensates the OB level by using OB pixels output from the CCD image sensor. A block diagram of the OB loop and OB clamp circuit is shown in Figure 5.
PAGE 19
Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 The OB clamp level (digital output value) can be externally set through the serial interface by inputting the digital code to the OB clamp level register. The digital codes to be input and the corresponding OB clamp levels are shown in Table 4. Table 4.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com STANDBY MODE AND POWER TRIM FUNCTION For the purpose of saving power, the VSP2560/62/66 devices can be put into a standby mode through the serial interface control when the device is not in use. In this mode, all the functional blocks are disabled and the digital outputs are set to '0'. The consumption current drops to approximately 2 mA. Only 10 ms is required to restore the device from standby mode.
PAGE 21
Not Recommended for New Designs www.ti.com VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 VOLTAGE REFERENCE All reference voltages and bias currents used in these devices are created from internal bandgap circuitry. The VSP2560/62/66 have symmetrical, independent voltage references for each channel. Both channels of the CDS and the ADC use three primary reference voltages: REFP (1.5 V), REFN (1.0 V), and CM (1.25 V) of an individual reference. REFP and REFN are buffered on-chip.
PAGE 22
Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com Data (1) and Data (2) Update Here RLOAD SLOAD SCLK A0 SDATA A9 D0 D5 6-Bit Data (1) 10-Bit Address D0 D5 D0 6-Bit Data (2) D5 6-Bit Data (3) Figure 8. Continuous Writing Mode SERIAL INTERFACE REGISTER DESCRIPTION PRODUCT PREVIEW The serial interface command data format is shown in Table 5. Descriptions of each register are provided in the following sections. Table 5.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 Clk-Pol-Ctrl Register Description (Address = 000h) The Clk-Pol-Ctrl register selects the active polarity of CLPDM, CLPOB, and SHP/SHD, as shown in Table 6. Table 6.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 www.ti.com Clamp Register Description (Address = 004h) The clamp levels for the VSP2560/62/66 are shown in Table 10. Table 10.
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Not Recommended for New Designs VSP2560 VSP2562 VSP2566 www.ti.com SBES008 – AUGUST 2008 A-PGA Register Description (Address = 008h) The A-PGA register describes the CDS gain control, as shown in Table 13. Table 13. CDS Gain Control D2 D1 D0 ANALOG GAIN (dB) 0 0 0 0 (default) 0 0 1 6 0 1 0 12 0 1 1 18 1 1 1 –3 Power Register Description (Address = 009h) The power register describes the power control settings, as shown in Table 14.
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VSP2560 VSP2562 VSP2566 Not Recommended for New Designs SBES008 – AUGUST 2008 www.ti.com POWER SUPPLY, GROUNDING, AND DEVICE COUPLING RECOMMENDATIONS The VSP2560/62/66 incorporate a high-precision, high-speed ADC and analog circuitry that are vulnerable to any extraneous noise from the rails or elsewhere. For this reason, the VSP2560/62/66 should be treated as an analog component.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device VSP2560PTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 17.4 Pack Materials-Page 1 9.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.5 2.0 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VSP2560PTR LQFP PT 48 1000 333.2 345.9 28.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.