Datasheet

6VFC32
PRINCIPLES OF OPERATION
The VFC32 operates on a principle of charge balance. The
signal input current is equal to V
IN
/R
1
. This current is
integrated by input op amp and C
2
, producing a downward
ramping integrator output voltage. When the integrator out-
put ramps to the threshold of the comparator, the one-shot is
triggered. The 1mA reference current is switched to the
integrator input during the one-shot period, causing the
integrator output ramp upward. After the one-shot period,
the integrator again ramps downward.
The oscillation process forces a long-term balance of charge
(or average current) between the input signal current and the
reference current. The equation for charge balance is:
Where:
f
O
is the output frequency
t
OS
is the one-shot period, equal to
t
OS
= 7500 C
1
(Farads) (4)
The values suggested for R
1
and C
1
are chosen to produce a
25% duty cycle at full-scale frequency output. For full-scale
frequencies above 200kHz, the recommended values pro-
duce a 50% duty cycle.
FREQUENCY-TO-VOLTAGE CONVERSION
Figure 4 shows the VFC32 connected as a frequency-to-
voltage converter. The capacitive-coupled input network C
3
,
R
6
and R
7
allow standard 5V logic levels to trigger the
comparator input. The comparator triggers the one-shot on
the falling edge of the frequency input pulses. Threshold
voltage of the comparator is approximately –0.7V. For
frequency input waveforms less than 5V logic levels, the
R
6
/R
7
voltage divider can be adjusted to a lower voltage to
assure that the comparator is triggered.
The value of C
1
is chosen from Figure 2 according to the
full-scale input frequency. C
2
smooths the output voltage
waveform. Larger values of C
2
reduce the ripple in the
output voltage. Smaller values of C
2
allow the output voltage
to settle faster in response to a change in input frequency.
Resistor R
1
can be trimmed to achieve the desired output
voltage at the full-scale input frequency.
I
IN
= I
R(AVERAGE)
(2)
V
IN
R
1
= f
O
t
OS
(1mA)
(3)
1k 1M
Full Scale Fre
q
uenc
y
(
Hz
)
0.1µF
10nF
1nF
100pF
10pF
Capacitor Value
10k 100k
C
2
R
1
= 20kΩ
66,000pF
f
FS (kHz)
Above 200kHz Full-Scale
C
1
= – 30pF
R
1
= 40kΩ
33,000pF
f
FS (kHz)
C
1
= – 30pF
FIGURE 2. Capacitor Value Selection.
FIGURE 3. Gain and Offset Voltage Trim Circuit.
Pinout shown is for
DIP and SOIC packages.
V
IN
One-Shot
13
10
12
+15V
7
11
f
O
V
INT
C
2
0.1µF
1
14
35kΩ
Gain Trim
4
–15V
5
C
1
33nF
+5V
4.7kΩ
VFC32
+15V
100kΩ
–15V
10MΩ
Offset
Trim
10kΩ
1mA