Datasheet

VFC320
6
SBVS017A
I
IN
max
The operation of the VFC320 as a highly linear frequency-
to-voltage converter, follows the same theory of operation as
the voltage-to-frequency converter. e
1
and e
2
are shorted and
F
IN
is disconnected from V
OUT
. F
IN
is then driven with a
signal which is sufficient to trigger comparator A. The one-
shot period will then be determined by C
1
as before, but the
cycle repetition frequency will be dictated by the digital
input at F
IN
.
DUTY CYCLE
The duty cycle (D) of the VFC is the ratio of the one-shot
period (t
2
) or pulse width, PW, to the total VFC period (t
1
+
t
2
). For the VFC320, t
2
is fixed and t
1
+ t
2
varies as the input
voltage. Thus the duty cycle, D, is a function of the input
voltage. Of particular interest is the duty cycle at full scale
frequency, D
FS
, which occurs at full scale input. D
FS
is a user
determined parameter which affects linearity.
D
t
tt
PW f
FS FS
=
+
=•
2
12
Best linearity is achieved when D
FS
is 25%. By reducing
equations (7) and (9) it can be shown that
D
FS
= =
Thus D
FS
= 0.25 corresponds to I
IN
max = 0.25mA.
INSTALLATION AND
OPERATING INSTRUCTIONS
VOLTAGE-TO-FREQUENCY CONVERSION
The VCF320 can be connected to operate as a V/F converter
that will accept either positive or negative input voltages, or
an input current. Refer to Figures 6 and 7.
FIGURE 7. Connection Diagram for V/F Conversion,
Negative Input Voltages.
EXTERNAL COMPONENT SELECTION
In general, the design sequence consists of: (1) choosing
f
MAX
, (2) choosing the duty cycle at full scale (D
FS
= 0.25
typically), (3) determining the input resistor, R
1
(Figure 4),
(4) calculating the one-shot capacitor, C
1
, (5) selecting the
integrator capacitor C
2
, and (6) selecting the output pull-up
resistor, R
2
.
Input Resistors R
1
and R
3
The input resistance (R
1
and R
3
in Figures 6 and 7) is
calculated to set the desired input current at full scale input
voltage. This is normally 0.25mA to provide a 25% duty
cycle at full scale input and output. Values other than D
FS
=
0.25 may be used but linearity will be affected.
The nominal value is R
1
is
R
1
=
If gain trimming is to be done, the nominal value is reduced
by the tolerance of C
1
and the desired trim range. R
1
should
have a very-low temperature coefficient since its drift adds
directly to the errors in the transfer function.
One-Shot Capacitor, C
1
This capacitor determines the duration of the one-shot pulse.
From equation (9) the nominal value is
C
1 NOM
=
For the usual 25% duty at f
MAX
= V
IN
/R
1
= 0.25mA there is
approximately 15pF of residual capacitance so that the
design value is
C
1
(pF) = – 15
(11)
(12)
(10)
V
IN
max / R
1
1mA 1mA
0.25mA
V
IN
max
V
IN
7.5 R
1
f
OUT
33 • 10
6
f
FS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
V
CC
(1)
NC
NC
NC
+V
CC
(1)
V
IN
C
2
Integrator Capacitor
Gain Adjustment
I
IN
R
3
R
1
R
5
R
4
+15V
15V
One-shot
Capacitor
C
1
R
2
+V
PU
f
OUT
NOTE:
(
1
)
B
y
pass with 0.01
µ
F
Pin numbers in squares
refer to DIP packa
g
e.
Offset Adj.
FIGURE 6. Connection Diagram for V/F Conversion,
Positive Input Voltages.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
V
CC
(1)
NC
NC
NC
+V
CC
(1)
C
2
Integrator Capacitor
Gain Adjustment
I
IN
R
1
R
3
R
5
R
4
+15V
15V
One-shot
capacitor
C
1
R
2
+V
PU
f
OUT
NOTE:
(
1
)
B
y
pass with 0.01
µ
F
Pin numbers in squares
refer to DIP package.
Offset Adj.
V
IN