Datasheet

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INPUT REGISTER BIT MAPS

VCA8500

SBOS390A – JANUARY 2008 – REVISED MARCH 2008

BYTE #1 BYTE #2 BYTE #3 BYTE #4 BYTE #5

D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39

Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8

Table 2. Default Register Configuration

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 0 0 0 1 1

Table 3. Byte 1 — Control Byte Register Map

BIT # NAME DESCRIPTION

D0 (LSB) 1 Start bit; must be a ‘ 1 ’ (high); 40-bit countdown starts with first falling clock edge.

D1 R/ W 1 = Write, 0 = Read; read prevents latching of new data/bits. Control register remains

latched with previously loaded data.

D2 PWR 1 = Power-down mode enabled (shutdown).

D3 BW Low-pass filter bandwidth setting (see Table 8 )

D4 CL Clamp level setting (see Table 8 )

D5 Mode 1 = TGC mode, 0 = CW doppler mode (TGC powered down)

D6 PG0 LSB of PGA gain control (see Table 9 )

D7 (MSB) PG1 MSB of PGA gain control

Table 4. Byte 2 — First Data Byte

BIT # NAME DESCRIPTION

D8 (LSB) DB1:1 Channel 1, LSB of matrix control

D9 DB1:2 Channel 1, matrix control

D10 DB1:3 Channel 1, matrix control

D11 DB1:4 Channel 1, MSB of matrix control

D12 DB2:1 Channel 2, LSB of matrix control

D13 DB2:2 Channel 2, matrix control

D14 DB2:3 Channel 2, matrix control

D15 (MSB) DB2:4 Channel 2; MSB of matrix control

Table 5. Byte 3 — Second Data Byte

BIT # NAME DESCRIPTION

D16 (LSB) DB3:1 Channel 3, LSB of matrix control

D17 DB3:2 Channel 3, matrix control

D18 DB3:3 Channel 3, matrix control

D19 DB3:4 Channel 3, MSB of matrix control

D20 DB4:1 Channel 4, LSB of matrix control

D21 DB4:2 Channel 4, matrix control

D22 DB4:3 Channel 4, matrix control

D23 (MSB) DB4:4 Channel 4, MSB of matrix control

Product Folder Link(s): VCA8500