Datasheet

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DEVICE INFORMATION
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VBL5
IN5
AVDD1
IN6
VBL6
VBL7
IN7
VBL8
IN8
AVDD2
VB2
VB6
VB4
V
REFH
V
REFL
AVDD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBL1
IN1
AVDD1
IN2
VBL2
VBL3
IN3
VBL4
IN4
V
CNTL
AVDD2
VB3
VB1
VB5
V
CM
OUT4
OUT4
OUT3
OUT3
OUT2
OUT2
OUT1
OUT1
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
64 63 62 61 60 59 58
57
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55 54
17
18 19 20
21 22
23
24
25 26
27
53 52 51 50 49
28 29 30 31 32
VCA8500
(GND)
PowerPAD
TM
AVDD1
PD
CW0
CW1
CW2
CW3
CW4 D_IN
CLK D_OUT
RST
DVDD
CW5
CW6
CW7
CW8
CW9
VCA8500
SBOS390A – JANUARY 2008 – REVISED MARCH 2008
RGC PACKAGE
QFN-64
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
PIN NO. NAME I/O DESCRIPTION
1 VBL1 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min)
2 IN1 I LNA input channel 1
3 AVDD1 +3.3V analog supply
4 IN2 I LNA input channel 2
5 VBL2 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min)
6 VBL3 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min)
7 IN3 I LNA input channel 3
8 VBL4 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min)
9 IN4 LNA input channel 4
10 V
CNTL
I Attenuator control voltage input (all channels)
11 AVDD2 +5V analog supply (VCA, CW)
12 VB3 Internal bias voltage (+4.2V); bypass with 0.1 µ F capacitor (min)
13 VB1 Internal bias voltage (+2.4V); bypass with 2.2 µ F capacitor (1.0 µ F min)
14 VB5 Internal bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min)
15 V
CM
Internal common-mode voltage (+1.65V); bypass with 0.1 µ F capacitor (min)
16 AVDD1 +3.3V analog supply
17 OUT4 O PGA output channel 4 (inverted)
18 OUT4 O PGA output channel 4
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