Datasheet

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APPLICATION INFORMATION
ANALOG INPUT AND LNA
A1
A2
To
Attenuator
8kW
8kW
7pF0.1mF
C
IN
³ m0.1 F
V
B
(+2.4V)
IN
V
BL
T/R
VCA8500
VCA8500
SBOS390A – JANUARY 2008 – REVISED MARCH 2008
This architecture minimizes any loading of the signal
source that may otherwise lead to a
frequency-dependent voltage divider. Moreover, the
While the LNA is designed as a fully differential
closed-loop design yields very low offsets and offset
amplifier, it is optimized to perform a single-ended
drift; this consideration is important because the LNA
input to differential output conversion. A simplified
directly drives the subsequent voltage-controlled
schematic of an LNA channel is shown in Figure 64 .
attenuator.
A bias voltage (V
B
) of +2.4V is internally applied to
The LNA of the VCA8500 uses the benefits of a
the LNA inputs through 8k Ω resistors. In addition, the
bipolar process technology to achieve an
dedicated signal input (IN pin) includes a pair of
exceptionally low-noise voltage of 0.7nV/ √ Hz, and a
back-to-back diodes that provide a coarse input
low current noise of only 3pA/ √ Hz. With these
clamping function in case the input signal rises to
input-referred noise specifications, the VCA8500
very large levels, exceeding 0.7V
PP
. This
achieves very low noise figure numbers over a wide
configuration prevents the LNA from being driven into
range of source resistances and frequencies (see
a severe overload state, which may otherwise cause
Figure 26 in the Typical Characteristics). The optimal
an extended overload recovery time. The integrated
noise power matching is achieved for source
diodes are designed to handle a dc current of up to
impedances of around 200 Ω .
approximately 5mA. Depending on the application
requirements, the system overload characteristics
Further details of the VCA8500 input and output
may be improved by adding external Schottky diodes
noise performance are shown in the Typical
at the LNA input, as shown in Figure 64 .
Characteristic graphs; the input-referred noise voltage
is derived by dividing the output-referred noise by the
As Figure 64 also shows, the complementary LNA
measured gain at each point along the gain control
input (V
BL
pin) is internally decoupled by a small
range.
capacitor. Furthermore, for each input channel, a
separate V
BL
pin is brought out for external
Noise Figure versus Source Resistance (R
S
)
bypassing. This bypassing should be done with a
small, 0.1 µ F (typical) ceramic capacitor placed in
R
S
( Ω ) NOISE FIGURE (dB)
close proximity to each V
BL
pin. Attention should be
50 2.21
given to provide a low-noise analog ground for this
200 1.10
bypass capacitor. A noisy ground potential may
400 1.14
cause noise to be picked up and injected into the
signal path, leading to higher noise levels.
1000 2.06
The LNA closed-loop architecture is internally
compensated for maximum stability without the need
of external compensation components (inductors or
capacitors). At the same time, the total input
capacitance is kept to a minimum with only 30pF.
Figure 64. LNA Channel (Simplified Schematic)
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Product Folder Link(s): VCA8500