Datasheet

www.ti.com
Input
CH1
(50mV/div)
Time(200ns/div)
PGA=20dB
V =1.7V
OUT PP
V =1V
CNTRL
Output
CH2
(0.5V/div)
Input
CH1
(22.4mV/div)
Time(200ns/div)
PGA=30dB
V =2.8V
OUT PP
V =1V
CNTRL
Output
CH2
(2.8V/div)
V
CH1
(0.5V/div)
CNTRL
Time(1 s/div)m
PGA=30dB
V =1V
OUT PP
Output
CH2
(0.5V/div)
PDPin
CH1
(1V/div)
Time(1ms/div)
Output
CH2
(0.2V/div)
PGA=20dB
V =1V
OUT PP
CNTRL
V =0.6V
VCA8500
SBOS390A JANUARY 2008 REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)
All specifications at T
A
= +25 ° C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1 µ F) input configuration
to the preamp (LNA), f
IN
= 5MHz, V
CNTL
= 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and R
LOAD
= 1k on each output to
ground, unless otherwise noted.
PGA OVERLOAD PGA OVERLOAD
(V
IN
= 50mV
PP
, Clamp Enabled) (V
IN
= 20mV
PP
)
Figure 56. Figure 57.
V
CNTRL
RESPONSE TIME POWER-DOWN RESPONSE TIME
Figure 58. Figure 59.
22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): VCA8500