Datasheet

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SERIAL DIGITAL INTERFACE (SDI)
TIMING INFORMATION
RST(Low)
CLK
DIN
D0(LSB)
D1 D2
D3
D4
D5 D6
D7(MSB)
t
5
t
4
t
1
t
2
t
3
SERIAL PORT TIMING TABLE
VCA8500
SBOS390A – JANUARY 2008 – REVISED MARCH 2008
• All writes and reads are five bytes at a time. Each byte consists of 8 bits, for a total instruction set of 40 bits.
• Data are latched on the falling edge of CLK.
• Separate write (DIN) and read data (DOUT) lines.
• Reads follow the same bitstream pattern seen in the write cycle.
• Reads extract data from the FIFO buffer, not the latched register.
• DOUT data are continuously available and do not need to be enabled with a read cycle. Selecting a read
cycle in the control register only prevents latching of data. The control register remains latched.
• The Reset pin (RST) must be low in order to allow the register to update with new data. RST can be held low
permanently. To initiate a reset cycle, pull the RST pin high for at least 100ns.
NOTE: This figure shows timing example for one data byte. A full register update cycle requires all five bytes (that is, 40 bits).
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
Serial CLK period 100 ns
t
2
Serial CLK HIGH time 40 ns
t
3
Serial CLK LOW time 40 ns
t
4
Data hold time 5 ns
t
5
Data setup time 5 ns
RST Reset pulse (L - H - L) 100 ns
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