Datasheet

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SBOS316D − JULY 2005 − REVISED OCTOBER 2008
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17
The ability to change the gain electronically offers
additional flexibility for optimizing the gain in order to
achieve either maximum signal-handling capability or
maximum sensitivity. Table 3 lists the input and output
signal-handling capability of the LNP.
Table 4 shows the voltage noise of the LNP for different
gain settings.
Table 3. Signal Handling Capability of LNP
GAIN
(dB)
G1, G2
MAX INPUT
(V
PP
Single-Ended)
MAX OUTPUT
(V
PP
Differential)
22 11 0.23 3.5
18 10 0.39 3.5
12 01 0.78 3.5
3 00 2.3 3.0
Table 4. LNP Gain vs Voltage Noise
LNP GAIN (dB)
VOLTAGE NOISE
(nV/√Hz
) at 5MHz
22 0.8
18 1.1
12 1.9
3 4.9
The current noise for the LNP is 1pA/√Hz for all gain
settings. The input capacitance of the LNP is 45pF.
The LNP output drives a buffer and a multiplexer (MUX)
along with a feedback network that can be used to program
the input impedance. Figure 56 shows a block diagram of
how these circuits are connected together. The output of
the LNP feeds a buffer to avoid the loading effect of the
feedback resistors and to achieve a more robust capability
for driving external circuits.
Buffer
LNP
VGA OUT
LNP OUT
VGA IN
MUX
IN
Feedback
Resistors
Figure 56. Block Diagram of LNP/VGA Interface
See Figure 57, which shows the response time of the LNP
gain changing from minimum to maximum.
Time (200ns/div)
LNP Gain
11
00
(10V/div)
LNP
Output
(500mV/div)
Figure 57. LNP Gain Change Response
The LNP also feeds a MUX, which accepts the LNP signal
or can receive an external signal. When applying an
external signal to the MUX (VCA
IN
), the signal should be
biased to a common-mode voltage in the range of 1.85V
to 3.15V. This biasing could be accomplished by using the
2.5V level of the V
CM
pin (19) of the VCA2615.
To MUX
(VGA
IN
)
V
CM
IN
Figure 58. Recommended Circuit for Coupling an
External Signal into the MUX
INPUT IMPEDANCE
Figure 59 shows a simplified schematic of the resistor
feedback network along with Table 5 that relates the FB1,
FB2, FB3 and FB4 code to the selected value. When the
selection bits leave the feedback network in the open
position, the input resistance of the LNP will become
100kΩ.
LNPIN OUT
1500
Ω
(FB1)
(FB2)
(FB3)
(FB4)
1000
Ω
500
Ω
250
Ω
Buffer
Figure 59. Feedback Resistor Network