Datasheet

8.0 Device Characteristics (Continued)
55
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USBN9603/USBN9604
Figure 26. Non-Multiplexed Mode Write Timing
(Consecutive Write Cycles Shown)
Note: The setup and hold times t
AS
and t
AH
are defined relative to the first transition of either CS or WR.
Both signals may switch at the same time.
8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01
B
)
(3.0V< V
CC
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
t
AH
ALE High Time
1
1. Clock Internal: CKI = 48 MHz on this device
C
L
= 50 pF 1/CKI nS
t
CLAL
Chip Select Low to ALE Low
C
L
= 50 pF 1/CKI nS
t
AVAL
Address Valid to ALE Low
C
L
=50pF 10 nS
t
AHAL
Address Hold after ALE Low
C
L
=50pF 10 nS
t
ALRH
ALE Low to RD High
2
2. Memory Clock: MCLK = CKI/4 = 12 MHz
C
L
= 50 pF 3/MCLK nS
t
RDLV
Read Low to Data Valid
C
L
=50pF 20 30 nS
t
RHDZ
Data Hold after Read High
C
L
=50pF 2 nS
t
RL
Read Pulse Width
C
L
= 50 pF 1/CKI nS
t
WHAH
Write High to next ALE High
C
L
= 50 pF 3/MCLK nS
t
WHCH
Write High to CS High
C
L
=50pF 10 nS
t
WL
Write Pulse Width
C
L
= 50 pF 1/CKI nS
t
DSWH
Data Setup to WR High
C
L
=50pF 5 nS
t
DHWH
Data Hold after WR High
C
L
=50pF 5 nS
A0
CS
D7-0 Input
ValidValid
WR
t
AS
t
DH
t
DS
t
WC
t
WW
t
AH
Obsolete