Datasheet

8.0 Device Characteristics (Continued)
54
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USBN9603/USBN9604
Note: CKI in the following tables refers to the internal clock of the device and not to the signal frequency applied at XIN.
8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00
B
)
(3.0V< V
CC
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
Figure 25. Non-Multiplexed Mode Read Timing
(Consecutive Read Cycles Shown)
Note: The setup time t
AS
is defined relative to the first transition of either CS or RD. Both signals
may switch at the same time.
Symbol Parameter Conditions Min Typ Max Units
t
AS
Address Setup Time
C
L
=50pF 0 nS
t
AH
Address Hold Time
C
L
=50pF 0 nS
t
RW
Read Pulse Width
1
1. Clock Internal: CKI = 48 MHz on this device
C
L
= 50 pF 1/CKI nS
t
RC
Read Cycle Time
23
2. Memory Clock: MCLK = CKI/4 = 12 MHz
3. Time until next read or write occurs
C
L
= 50 pF 3/MCLK nS
t
RDV
Data Output Valid after Read Low
C
L
=50pF 20 30 nS
t
RDH
Data Output Hold after Read High
C
L
=50pF 2 nS
t
WW
Write Pulse Width
1
C
L
= 50 pF 1/CKI nS
t
WC
Write Cycle Time
23
C
L
= 50 pF 3/MCLK nS
t
DS
Data Input Setup Time
C
L
=50pF 25 nS
t
DH
Data Input Hold Time
C
L
=50pF 8 nS
A0
CS
D7-0 Output
ValidValid
RD
t
AS
t
RDH
t
RDV
t
RC
t
RW
Obsolete