Datasheet

7.0 Register Set (Continued)
32
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7.1.4 Node Functional State Register (NFSR)
NFS
Node Functional State. The firmware should initiate all required state transitions according to the respective status bits in
the Alternate Event (ALTEV) register. The valid transitions are shown in Figure 18. The node functional state bits set the
node state, as shown in Table 6.
Table 6. USB Functional States
7.1.5 Main Event Register (MAEV)
WARN
One of the unmasked bits in the FIFO Warning Event (FWEV) register has been set. This bit is cleared by reading the FWEV
register.
ALT
Alternate. One of the unmasked ALTEV register bits has been set. This bit is cleared by reading the ALTEV register.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Reserved NFS1-0
-00
- r/w
NFS
Node State Description
10
0 0 NodeReset This is the USB Reset state. This is entered upon a module
reset or by software upon detection of a USB Reset. Upon entry,
all endpoint pipes are disabled. DEF in the Endpoint Control 0
(EPC0) register and AD_EN in the Function Address (FAR)
register should be cleared by software on entry to this state. On
exit, DEF should be reset so the device responds to the default
address.
0 1 NodeResume In this state, resume "K" signalling is generated. This state
should be entered by firmware to initiate a remote wake-up
sequence by the device. The node must remain in this state for
at least 1 mS and no more than 15 mS.
1 0 NodeOperational This is the normal operational state. In this state the node is
configured for operation on the USB bus.
1 1 NodeSuspend Suspend state should be entered by firmware on detection of a
Suspend event while in Operational state. While in Suspend
state, the transceivers operate in their low-power suspend mode.
All endpoint controllers and the bits TX_EN, LAST and RX_EN
are reset, while all other internal states are frozen. On detection
of bus activity, the RESUME bit in the ALTEV register is set. In
response, software can cause entry to NodeOperational state.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN
00 000 000
see text r CoR r CoR r r r
Obsolete