Datasheet

6.0 Functional Description (Continued)

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USBN9603/USBN9604

Table 4. USBN9603/4 Endpoint FIFO Sizes

If two endpoints in the same direction are programmed with the same endpoint number and both are enabled, data is re-

ceived or transmitted to/from the endpoint with the lower number, until that endpoint is disabled for bulk or interrupt transfers,

or becomes full or empty for ISO transfers. For example, if receive EP2 and receive EP4 both use endpoint 5 and are both

isochronous, the first OUT packet is received into EP2 and the second OUT packet into EP4, assuming no firmware inter-

action inbetween. For ISO endpoints, this allows implementing a ping-pong buffer scheme together with the frame number

match logic.

Endpoints in different directions programmed with the same endpoint number operate independently.

Bidirectional Control Endpoint FIFO0 Operation

FIFO0 should be used for the bidirectional control endpoint zero. It can be configured to receive data sent to the default

address with the DEF bit in the EPC0 register. Isochronous transfers are not supported for the control endpoint.

The Endpoint 0 FIFO can hold a single receive or transmit packet with up to 8 bytes of data. Figure 20 shows the basic

operation in both receive and transmit direction.

Note: The actual current operating state is not directly visible to the user.

Endpoint No.

TX FIFO RX FIFO

Size (Bytes) Name Size (Bytes) Name

0 8 FIFO0

1 64 TXFIFO1

2 64 RXFIFO1

3 64 TXFIFO2

4 64 RXFIFO2

5 64 TXFIFO3

6 64 RXFIFO3

Figure 20. Endpoint 0 Operation

TXFILL

TXWAIT

RXWAIT

IDLE

Write to TXD0

TX_EN Bit,

RX_EN Bit, RXC0 Register

OUT or

SETUP Token

FIFO0 Empty

FLUSH Bit, RXC0 Register

FLUSH Bit TXC0 Register

IN token

(*) For zero length packet, TX_EN causes a transition from IDLE to TXWAIT

Transmission

Done

(All Data Read)

TXC0 Register (*)

Obsolete