Datasheet

3.0 Parallel Interface (Continued)
15
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USBN9603/USBN9604
3.2 MULTIPLEXED MODE
Multiplexed mode uses the control pins
CS, RD, WR, the address latch enable signal ALE and the bidirectional address data
bus AD7-0 as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to V
CC
. The address is latched
into the ADDR register when ALE is high. Data is output/input with the next active
RD or WR signal. All registers are directly
accessible in this interface mode.
Figure 7 shows basic timing of the interface in Multiplexed mode.
CS
WR
0x00
0x3F
AD7-0
RD
Data Out
Data In
Register File
ADDR
EN
Address
Figure 6. Multiplexed Mode Block Diagram
ALE
ALE
CS
AD7-0
DATA
RD or WR
ADDR
Figure 7. Multiplexed Mode Basic Read/Write Timing
Obsolete